neat verilog thing

wally-pipelined/src/ebu/ahblite.sv

@@ -30,6 +30,10 @@
 
 `include "wally-config.vh"
 
+package ahbliteState;
+  typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE, MMUIDLE} statetype;
+endpackage
+
 module ahblite (
   input  logic             clk, reset,
   input  logic             StallW, FlushW,
@@ -90,7 +94,7 @@ module ahblite (
   // Data accesses have priority over instructions.  However, if a data access comes
   // while an instruction read is occuring, the instruction read finishes before
   // the data access can take place.
-  typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE, MMUIDLE} statetype;
+  import ahbliteState::*;
   statetype BusState, NextBusState;
 
   flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);

wally-pipelined/testbench/testbench-busybear.sv

@@ -191,9 +191,10 @@ module testbench_busybear();
 
   logic [`XLEN-1:0] readAdrExpected;
 
+  import ahbliteState::*;
   always @(dut.HRDATA) begin
     #2;
-    if (dut.hart.MemRWM[1] && ~HWRITE && HADDR[31:3] != dut.PCF[31:3] && dut.HRDATA !== {64{1'bx}}) begin
+    if (dut.hart.MemRWM[1] && ~HWRITE && dut.hart.ebu.BusState == MEMREAD && dut.HRDATA !== {64{1'bx}}) begin
       //$display("%0t", $time);
       if($feof(data_file_memR)) begin
         $display("no more memR data to read");