cvw/wally-pipelined
Ross Thompson d8ab7a5de2 Partially working icache.
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
..
bin
config buildroot: sim is now running! 2021-04-17 14:44:32 -04:00
misc/tlb_toy Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
ppa Config file for ppa experiments 2021-03-25 10:23:21 -05:00
regression Partially working icache. 2021-04-22 10:20:36 -05:00
src Partially working icache. 2021-04-22 10:20:36 -05:00
testbench Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
testgen Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
lint-wally Why was the linter messed up? 2021-04-20 22:06:12 -05:00