forked from Github_Repos/cvw
Add privileged tests for mcause
This commit is contained in:
Domenico Ottolia
parent
1ceb7a7431
commit
82ea97e304
@ -30,33 +30,149 @@ from random import getrandbits
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# # exit(1)
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def randRegs():
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reg1 = randint(1,31)
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reg2 = randint(1,31)
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reg3 = randint(1,31)
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reg1 = randint(1,30)
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reg2 = randint(1,30)
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reg3 = randint(1,30)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return reg1, reg2, reg3
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def writeVectors(storecmd):
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global testnum
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reg1, reg2, reg3 = randRegs()
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# t5 gets written with mtvec?
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# lines = f"""
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# li x{reg1}, 0
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# csrwi mtvec, 80002000
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# .data 00000000
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# j _done{testnum}
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# _trap{testnum}:
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# csrrs x{reg1}, mcause, x0
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# ecall
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# _done{testnum}:
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# add x0, x0, x0
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# """
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#lines =
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lines = f"""
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li x{reg1}, 0
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j _setup
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csrrs x31, mcause, x0
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ecall
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_setup:
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li x2, 0x80000004
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csrrw x0, mtvec, x2
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"""
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f.write(lines)
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write(lines, storecmd, reg1, 0)
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# User Software Interrupt
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write(f"""
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li x3, 0x8000000
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{storecmd} x2, 0(x3)
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""", storecmd, True, 0, "u")
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def write(lines, storecmd, reg, expected):
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# Supervisor Software Interrupt
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write(f"""
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li x3, 0x8000000
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{storecmd} x2, 0(x3)
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""", storecmd, True, 0, "s")
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# Machine Software Interrupt
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write(f"""
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li x3, 0x8000000
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{storecmd} x2, 0(x3)
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""", storecmd, True, 3)
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# User Timer Interrupt
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#write(f"""
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# lw x2, mtimecmp
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# {storecmd} x2, mtimecmp
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#""", storecmd, True, 4, "u")
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# # Supervisor Timer Interrupt
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#write(f"""
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# lw x2, mtimecmp
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# {storecmd} x2, mtimecmp
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#""", storecmd, True, 5, "s")
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# Machine Timer Interrupt
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#write(f"""
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# lw x2, mtimecmp
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# {storecmd} x2, mtimecmp
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#""", storecmd, True, 6)
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# User external interrupt True, 8
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# Supervisor external interrupt True, 9
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# Instr Addr Misalign
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write(f"""
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li x2, 0x00000000
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lw x3, 11(x2)
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""", storecmd, False, 0)
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# Instr Access Fault False, 1
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# Not possible in machine mode, because we can access all memory
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# Illegal Instruction
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write(f"""
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.data 00000000
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""", storecmd, False, 2)
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# Breakpoint
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write(f"""
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ebreak
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""", storecmd, False, 3)
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# Load Addr Misalign
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write(f"""
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li x2, 0x00000000
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lw x3, 11(x2)
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""", storecmd, False, 4)
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# Load Access Fault False, 5
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# Not possible in machine mode, because we can access all memory
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# Store/AMO address misaligned
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write(f"""
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li x2, 0x00000000
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{storecmd} x3, 11(x2)
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""", storecmd, False, 6)
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# Store/AMO access fault False, 7
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# Not possible in machine mode, because we can access all memory
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# Environment call from U-mode
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# Environment call from S-mode
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def write(lines, storecmd, interrupt, code, mode = "m"):
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global testnum
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# generate expected interrupt code
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expected = (0 if not interrupt else (2**31 if xlen == 32 else 2**63)) + code
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lines = f"""
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# Testcase {testnum}
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li x31, 0
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{lines}
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{storecmd} x{reg}, {str(wordsize*testnum)}(x6)
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#RVTEST_IO_ASSERT_GPR_EQ(x0, 0, {formatstr.format(expected)})
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{storecmd} x31, {str(wordsize*testnum)}(x6)
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# RVTEST_IO_ASSERT_GPR_EQ(x0, 0, {formatstr.format(expected)})
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"""
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#if mode == "s":
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# go to supervisor mode
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#elif mode == "u":
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# go to user mode
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f.write(lines)
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if (xlen == 32):
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@ -71,31 +187,31 @@ def write(lines, storecmd, reg, expected):
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##################################
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# name: (interrupt?, code)
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tests = {
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'User software interrupt': (1, '0'),
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'Supervisor software interrupt': (1, '1'),
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'Machine software interrupt': (1, '3'),
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'User timer interrupt': (1, '4'),
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'Supervisor timer interrupt': (1, '5'),
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'Machine timer interrupt': (1, '7'),
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'User external interrupt': (1, '8'),
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'Supervisor external interrupt': (1, '9'),
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'Machine external interrupt': (1, '11'),
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'Instruction address misaligned': (0, '0'),
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'Instruction access fault': (0, '1'),
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'Illegal instruction': (0, '2'),
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'Breakpoint': (0, '3'),
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'Load address misaligned': (0, '4'),
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'Load access fault': (0, '5'),
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'Store/AMO address misaligned': (0, '6'),
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'Store/AMO access fault': (0, '7'),
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'Environment call from U-mode': (0, '8'),
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'Environment call from S-mode': (0, '9'),
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'Environment call from M-mode': (0, '11'),
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'Instruction page fault': (0, '12'),
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'Load page fault': (0, '13'),
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'Store/AMO page fault': (0, '15'),
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}
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# tests = {
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# 'User software interrupt': (1, '0'),
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# 'Supervisor software interrupt': (1, '1'),
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# 'Machine software interrupt': (1, '3'),
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# 'User timer interrupt': (1, '4'),
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# 'Supervisor timer interrupt': (1, '5'),
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# 'Machine timer interrupt': (1, '7'),
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# 'User external interrupt': (1, '8'),
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# 'Supervisor external interrupt': (1, '9'),
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# 'Machine external interrupt': (1, '11'),
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# 'Instruction address misaligned': (0, '0'),
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# 'Instruction access fault': (0, '1'),
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# 'Illegal instruction': (0, '2'),
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# 'Breakpoint': (0, '3'),
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# 'Load address misaligned': (0, '4'),
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# 'Load access fault': (0, '5'),
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# 'Store/AMO address misaligned': (0, '6'),
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# 'Store/AMO access fault': (0, '7'),
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# 'Environment call from U-mode': (0, '8'),
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# 'Environment call from S-mode': (0, '9'),
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# 'Environment call from M-mode': (0, '11'),
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# 'Instruction page fault': (0, '12'),
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# 'Load page fault': (0, '13'),
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# 'Store/AMO page fault': (0, '15'),
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# }
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 60;
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@ -132,23 +248,23 @@ for xlen in xlens:
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f.write(line)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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# h = open("../testgen_header.S", "r")
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# for line in h:
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# f.write(line)
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# print directed and random test vectors
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writeVectors(storecmd)
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# h = open("../testgen_footer.S", "r")
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# for line in h:
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# f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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# lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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# lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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# f.write(lines)
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f.close()
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r.close()
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