Cleaned up some unused signals

wally-pipelined/src/dmem/dmem.sv

@@ -59,8 +59,7 @@ module dmem (
   input logic  [`XLEN-1:0] PageTableEntryM,
   input logic  [1:0]       PageTypeM,
   input logic  [`XLEN-1:0] SATP_REGW,
-  input logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-  input logic [1:0]        STATUS_MPP, 
+  input logic              STATUS_MXR, STATUS_SUM,
   input logic              DTLBWriteM, DTLBFlushM,
   output logic             DTLBMissM, DTLBHitM,
   
@@ -75,7 +74,6 @@ module dmem (
   output  logic            PMALoadAccessFaultM, PMAStoreAccessFaultM,
   output  logic            PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
   
-  output logic             DCacheableM, DIdempotentM, DAtomicAllowedM,
   output logic             DSquashBusAccessM,
   output logic [5:0]       DHSELRegionsM
   
@@ -102,7 +100,6 @@ module dmem (
                 .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM),
 
                 .ExecuteAccessF(1'b0),
-                .Cacheable(DCacheableM), .Idempotent(DIdempotentM), .AtomicAllowed(DAtomicAllowedM),
                 .SquashBusAccess(DSquashBusAccessM), .HSELRegions(DHSELRegionsM),
                 .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
 
@@ -188,8 +185,6 @@ module dmem (
       default: NextState = STATE_READY;
     endcase // case (CurrState)
   end
-  
-  
 
 endmodule
 

wally-pipelined/src/ifu/ifu.sv

@@ -70,8 +70,7 @@ module ifu (
   input logic  [`XLEN-1:0] PageTableEntryF,
   input logic  [1:0]       PageTypeF,
   input logic  [`XLEN-1:0] SATP_REGW,
-  input logic              STATUS_MXR, STATUS_SUM,  STATUS_MPRV,
-  input logic  [1:0]       STATUS_MPP, // *** the last two are for the pmp checker.
+  input logic              STATUS_MXR, STATUS_SUM, 
   input logic              ITLBWriteF, ITLBFlushF,
   output logic             ITLBMissF, ITLBHitF,
 
@@ -84,7 +83,6 @@ module ifu (
   input  logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker.
 
   output logic             PMPInstrAccessFaultF, PMAInstrAccessFaultF,
-  output logic             ICacheableF, IIdempotentF, IAtomicAllowedF,
   output logic             ISquashBusAccessF,
   output logic [5:0]       IHSELRegionsF
 
@@ -113,7 +111,6 @@ module ifu (
                 .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF),
 
                 .AtomicAccessM(1'b0), .WriteAccessM(1'b0), .ReadAccessM(1'b0), // *** is this the right way force these bits constant? should they be someething else?
-                .Cacheable(ICacheableF), .Idempotent(IIdempotentF), .AtomicAllowed(IAtomicAllowedF),
                 .SquashBusAccess(ISquashBusAccessF), .HSELRegions(IHSELRegionsF),
                 .*);
 

wally-pipelined/src/mmu/cam_line.sv

@@ -32,7 +32,7 @@ module cam_line #(parameter KEY_BITS = 20,
                   parameter HIGH_SEGMENT_BITS = 10) (
   input                 clk, reset,
 
-  // input to scheck which SvMode is running
+  // input to check which SvMode is running
   input [`SVMODE_BITS-1:0] SvMode,
   
   // The requested page number to compare against the key

wally-pipelined/src/mmu/mmu.sv

@@ -69,12 +69,9 @@ module mmu #(parameter ENTRY_BITS = 3,
   input  logic [2:0]       HSIZE, HBURST,
   input  logic             HWRITE,
   input  logic             AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
-  input  logic             STATUS_MPRV,
-  input  logic [1:0]       STATUS_MPP,
   input  logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
   input  logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker.
 
-  output logic             Cacheable, Idempotent, AtomicAllowed,
   output logic             SquashBusAccess, // *** send to privileged unit
   output logic             PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM,
   output logic             PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM,
@@ -83,7 +80,7 @@ module mmu #(parameter ENTRY_BITS = 3,
 );
 
   logic PMPSquashBusAccess, PMASquashBusAccess;
-
+  logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here.
   // Translation lookaside buffer
 
   tlb #(.ENTRY_BITS(ENTRY_BITS), .ITLB(IMMU)) tlb(.*);

wally-pipelined/src/mmu/pmpchecker.sv

@@ -36,9 +36,6 @@ module pmpchecker (
 
   input  logic [1:0]       PrivilegeModeW,
 
-  input  logic [1:0]       STATUS_MPP,
-  input  logic             STATUS_MPRV,
-
   input  logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW,
 
   // *** ModelSim has a switch -svinputport which controls whether input ports

wally-pipelined/src/privileged/privileged.sv

@@ -66,8 +66,7 @@ module privileged (
   output logic		   IllegalFPUInstrE,
   output logic [1:0]       PrivilegeModeW,
   output logic [`XLEN-1:0] SATP_REGW,
-  output logic             STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-  output logic [1:0]       STATUS_MPP, 
+  output logic             STATUS_MXR, STATUS_SUM,
   output logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW,
   output logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], //*** to be sent up through wallypipelinedhart into the pma/pmp in ifu and dmem. *** is it a bad idea to have this huge bus running all over?
   output logic [2:0]       FRM_REGW,
@@ -96,7 +95,8 @@ module privileged (
   logic MTrapM, STrapM, UTrapM;
   logic InterruptM; 
 
-  logic       STATUS_SPP, STATUS_TSR;
+  logic [1:0] STATUS_MPP;
+  logic       STATUS_SPP, STATUS_TSR, STATUS_MPRV; // **** status mprv is unused outside of the csr module as of 4 June 2021. should it be deleted alltogether from the module, or should I leav the pin here in case someone needs it? 
   logic       STATUS_MIE, STATUS_SIE;
   logic [11:0] MIP_REGW, MIE_REGW;
   logic md, sd;

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -110,16 +110,13 @@ module wallypipelinedhart (
   logic             ITLBMissF, ITLBHitF;
   logic             DTLBMissM, DTLBHitM;
   logic [`XLEN-1:0] SATP_REGW;
-  logic             STATUS_MXR, STATUS_SUM, STATUS_MPRV;
-  logic [1:0]       PrivilegeModeW, STATUS_MPP;
-
+  logic             STATUS_MXR, STATUS_SUM;
+  logic [1:0]       PrivilegeModeW;
   logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM;
   logic [1:0]       PageTypeF, PageTypeM;
 
   // PMA checker signals
   logic             AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM;
-  logic             DCacheableM, DIdempotentM, DAtomicAllowedM;
-  logic             ICacheableF, IIdempotentF, IAtomicAllowedF;
   logic             PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM;
   logic             PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
   logic             DSquashBusAccessM, ISquashBusAccessF;