forked from Github_Repos/cvw
rv64 interrupt servicing
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@ -49,13 +49,13 @@ module csri #(parameter
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// assumes no N-mode user interrupts
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always_comb begin
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IntInM = 0; // *** does this really work
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IntInM[11] = ExtIntM & ~MIDELEG_REGW[9]; // MEIP
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IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP
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IntInM[7] = TimerIntM & ~MIDELEG_REGW[5]; // MTIP
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IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP
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IntInM[3] = SwIntM & ~MIDELEG_REGW[1]; // MSIP
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IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP
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IntInM = 0; // *** does this overwriting technique really synthesize
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IP_REGW[11] = ExtIntM & ~MIDELEG_REGW[9]; // MEIP
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IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP
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IntInM[7] = TimerIntM & ~MIDELEG_REGW[5]; // MTIP
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IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP
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IntInM[3] = SwIntM & ~MIDELEG_REGW[1]; // MSIP
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IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP
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end
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// Interrupt Write Enables
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@ -77,14 +77,14 @@ module csri #(parameter
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assign SIP_WRITE_MASK = 12'h000;
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end
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always @(posedge clk, posedge reset) begin
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if (reset) IP_REGW <= 12'b0;
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else if (WriteMIPM) IP_REGW <= (CSRWriteValM & MIP_WRITE_MASK) | IntInM; // MTIP unclearable
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else if (WriteSIPM) IP_REGW <= (CSRWriteValM & SIP_WRITE_MASK) | IntInM; // MTIP unclearable
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if (reset) IP_REGW[9:0] <= 10'b0;
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else if (WriteMIPM) IP_REGW[9:0] <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
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else if (WriteSIPM) IP_REGW[9:0] <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
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// else if (WriteUIPM) IP_REGW = (CSRWriteValM & 12'hBBB) | (NextIPM & 12'h080); // MTIP unclearable
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else IP_REGW <= IP_REGW | IntInM; // *** check this turns off interrupts properly even when MIDELEG changes
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else IP_REGW[9:0] <= IP_REGW[9:0] | IntInM[9:0]; // *** check this turns off interrupts properly even when MIDELEG changes
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end
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always @(posedge clk, posedge reset) begin
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if (reset) IE_REGW <= 12'b0;
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if (reset) IE_REGW <= 12'b0;
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else if (WriteMIEM) IE_REGW <= (CSRWriteValM & 12'hAAA); // MIE controls M and S fields
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else if (WriteSIEM) IE_REGW <= (CSRWriteValM & 12'h222) | (IE_REGW & 12'h888); // only S fields
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// else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
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@ -49,7 +49,7 @@ module trap (
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logic InterruptM;
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// Determine pending enabled interrupts
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assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
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assign MIntGlobalEnM = {12{(PrivilegeModeW != `M_MODE) || STATUS_MIE}}; // if M ints enabled or lower priv 3.1.9
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assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
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assign PendingIntsM = (MIP_REGW & MIE_REGW) & ((MIntGlobalEnM & 12'h888) | (SIntGlobalEnM & 12'h222));
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assign InterruptM = |PendingIntsM; // interrupt if any sources are pending
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@ -41,13 +41,15 @@ module uart (
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// UART interface signals
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logic [2:0] A;
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logic MEMRb, MEMWb;
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logic MEMRb, MEMWb, memread, memwrite;
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logic [7:0] Din, Dout;
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// rename processor interface signals to match PC16550D and provide one-byte interface
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flopr #(1) memreadreg(HCLK, ~HRESETn, ~(HSELUART & ~HWRITE), MEMRb);
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flopr #(1) memwritereg(HCLK, ~HRESETn, ~(HSELUART & HWRITE), MEMWb);
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flopr #(1) memreadreg(HCLK, ~HRESETn, (HSELUART & ~HWRITE), memread);
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flopr #(1) memwritereg(HCLK, ~HRESETn, (HSELUART & HWRITE), memwrite);
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flopr #(3) haddrreg(HCLK, ~HRESETn, HADDR[2:0], A);
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assign MEMRb = ~memread;
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assign MEMWb = ~memwrite;
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assign HRESPUART = 0; // OK
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assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something
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@ -352,7 +352,7 @@ module testbench();
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};
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string tests64periph[] = '{
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"rv64i-periph/WALLY-PLIC", "2000"
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"rv64i-periph/WALLY-PLIC", "2080"
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};
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string tests32periph[] = '{
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@ -402,7 +402,7 @@ module testbench();
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if (TESTSPERIPH) begin
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tests = tests32periph;
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end else begin
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tests = {tests32i,tests32periph};
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tests = {tests32i};//,tests32periph}; *** broken at the moment
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if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
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else tests = {tests, tests32iNOc};
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if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
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@ -1,413 +0,0 @@
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///////////////////////////////////////////
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// testbench-imperas.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs from the Imperas suite
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module testbench();
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parameter DEBUG = 0;
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parameter TESTSBP = 0;
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logic clk;
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logic reset;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[0:10000];
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logic [`XLEN-1:0] signature[0:10000];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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string tests64i[] = {
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"peripherals/WALLY-PLIC", "2000"
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//"peripherals/WALLY-UART", "2000"
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};
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string tests64ic[] = {
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};
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string tests64iNOc[] = {
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};
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string tests64m[] = {
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};
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string tests64a[] = {
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};
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string tests32a[] = {
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};
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string tests32m[] = {
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};
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string tests32ic[] = {
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};
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string tests32iNOc[] = {
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};
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string tests32i[] = {
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};
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string testsBP64[] = {
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};
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string tests64p[] = {
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};
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string tests[];
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string ProgramAddrMapFile, ProgramLabelMapFile;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`XLEN-1:0] PCW;
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
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// pick tests based on modes supported
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initial begin
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if (`XLEN == 64) begin // RV64
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if (TESTSBP) begin
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tests = testsBP64;
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end else begin
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tests = {tests64i};
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if (`C_SUPPORTED) tests = {tests, tests64ic};
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else tests = {tests, tests64iNOc};
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if (`M_SUPPORTED) tests = {tests, tests64m};
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// if (`F_SUPPORTED) tests = {tests64f, tests};
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// if (`D_SUPPORTED) tests = {tests64d, tests};
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if (`A_SUPPORTED) tests = {tests, tests64a};
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end
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// tests = {tests64a, tests};
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tests = {tests, tests64p};
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end else begin // RV32
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// *** add the 32 bit bp tests
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tests = {tests32i};
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if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
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else tests = {tests, tests32iNOc};
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if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
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// if (`F_SUPPORTED) tests = {tests32f, tests};
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if (`A_SUPPORTED) tests = {tests, tests32a};
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end
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// tests = tests64p;
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end
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string signame, memfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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wallypipelinedsoc dut(.*);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.ic.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName,
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InstrEName, InstrMName, InstrWName);
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// initialize tests
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initial
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begin
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test = 0;
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totalerrors = 0;
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testadr = 0;
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// fill memory with defined values to reduce Xs in simulation
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if (`XLEN == 32) meminit = 32'hFEDC0123;
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else meminit = 64'hFEDCBA9876543210;
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for (i=0; i<=65535; i = i+1) begin
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//dut.imem.RAM[i] = meminit;
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// dut.uncore.RAM[i] = meminit;
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end
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// read test vectors into memory
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
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$display("Read memfile %s", memfilename);
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reset = 1; # 42; reset = 0;
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end
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// generate clock to sequence tests
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always
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begin
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clk = 1; # 5; clk = 0; # 5;
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end
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// check results
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always @(negedge clk)
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begin
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if (dut.hart.priv.EcallFaultM &&
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(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin
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$display("Code ended with ecall with gp = 1");
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#60; // give time for instructions in pipeline to finish
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// clear signature to prevent contamination from previous tests
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for(i=0; i<10000; i=i+1) begin
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sig32[i] = 'bx;
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end
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// read signature, reformat in 64 bits if necessary
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signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
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$readmemh(signame, sig32);
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i = 0;
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while (i < 10000) begin
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if (`XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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end else begin
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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end
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end
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// Check errors
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i = 0;
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errors = 0;
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if (`XLEN == 32)
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testadr = (`TIMBASE+tests[test+1].atohex())/4;
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else
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testadr = (`TIMBASE+tests[test+1].atohex())/8;
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/* verilator lint_off INFINITELOOP */
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while (signature[i] !== 'bx) begin
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//$display("signature[%h] = %h", i, signature[i]);
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if (signature[i] !== dut.uncore.dtim.RAM[testadr+i]) begin
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if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
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// report errors unless they are garbage at the end of the sim
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// kind of hacky test for garbage right now
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
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tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
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end
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end
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i = i + 1;
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) $display("%s succeeded. Brilliant!!!", tests[test]);
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else begin
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$display("%s failed with %d errors. :(", tests[test], errors);
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totalerrors = totalerrors+1;
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end
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test = test + 2;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$stop;
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end
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else begin
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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$display("Read memfile %s", memfilename);
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ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
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reset = 1; # 17; reset = 0;
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end
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end
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end // always @ (negedge clk)
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// track the current function or global label
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if (DEBUG == 1) begin : functionRadix
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function_radix function_radix(.reset(reset),
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.ProgramAddrMapFile(ProgramAddrMapFile),
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.ProgramLabelMapFile(ProgramLabelMapFile));
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end
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// initialize the branch predictor
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initial begin
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
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end
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endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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module instrTrackerTB(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrF, InstrD,
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input logic [31:0] InstrE, InstrM,
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input logic [31:0] InstrW,
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// output logic [31:0] InstrW,
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output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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// flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB fdec(InstrF, InstrFName);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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instrNameDecTB wdec(InstrW, InstrWName);
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endmodule
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// decode the instruction name, to help the test bench
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module instrNameDecTB(
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input logic [31:0] instr,
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output string name);
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logic [6:0] op;
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logic [2:0] funct3;
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logic [6:0] funct7;
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logic [11:0] imm;
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assign op = instr[6:0];
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assign funct3 = instr[14:12];
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assign funct7 = instr[31:25];
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assign imm = instr[31:20];
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// it would be nice to add the operands to the name
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// create another variable called decoded
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always_comb
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casez({op, funct3})
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10'b0000000_000: name = "BAD";
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10'b0000011_000: name = "LB";
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10'b0000011_001: name = "LH";
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10'b0000011_010: name = "LW";
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10'b0000011_011: name = "LD";
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10'b0000011_100: name = "LBU";
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10'b0000011_101: name = "LHU";
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10'b0000011_110: name = "LWU";
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10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
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else name = "ADDI";
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10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
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else name = "ILLEGAL";
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10'b0010011_010: name = "SLTI";
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10'b0010011_011: name = "SLTIU";
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10'b0010011_100: name = "XORI";
|
||||
10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
|
||||
else if (funct7[6:1] == 6'b010000) name = "SRAI";
|
||||
else name = "ILLEGAL";
|
||||
10'b0010011_110: name = "ORI";
|
||||
10'b0010011_111: name = "ANDI";
|
||||
10'b0010111_???: name = "AUIPC";
|
||||
10'b0100011_000: name = "SB";
|
||||
10'b0100011_001: name = "SH";
|
||||
10'b0100011_010: name = "SW";
|
||||
10'b0100011_011: name = "SD";
|
||||
10'b0011011_000: name = "ADDIW";
|
||||
10'b0011011_001: name = "SLLIW";
|
||||
10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
|
||||
else if (funct7 == 7'b0100000) name = "SRAIW";
|
||||
else name = "ILLEGAL";
|
||||
10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
|
||||
else if (funct7 == 7'b0100000) name = "SUBW";
|
||||
else if (funct7 == 7'b0000001) name = "MULW";
|
||||
else name = "ILLEGAL";
|
||||
10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
|
||||
else if (funct7 == 7'b0000001) name = "DIVW";
|
||||
else name = "ILLEGAL";
|
||||
10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
|
||||
else if (funct7 == 7'b0100000) name = "SRAW";
|
||||
else if (funct7 == 7'b0000001) name = "DIVUW";
|
||||
else name = "ILLEGAL";
|
||||
10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
|
||||
else name = "ILLEGAL";
|
||||
10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
|
||||
else if (funct7 == 7'b0000001) name = "MUL";
|
||||
else if (funct7 == 7'b0100000) name = "SUB";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
|
||||
else if (funct7 == 7'b0000001) name = "MULH";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
|
||||
else if (funct7 == 7'b0000001) name = "MULHSU";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
|
||||
else if (funct7 == 7'b0000001) name = "MULHU";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
|
||||
else if (funct7 == 7'b0000001) name = "DIV";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
|
||||
else if (funct7 == 7'b0000001) name = "DIVU";
|
||||
else if (funct7 == 7'b0100000) name = "SRA";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
|
||||
else if (funct7 == 7'b0000001) name = "REM";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
|
||||
else if (funct7 == 7'b0000001) name = "REMU";
|
||||
else name = "ILLEGAL";
|
||||
10'b0110111_???: name = "LUI";
|
||||
10'b1100011_000: name = "BEQ";
|
||||
10'b1100011_001: name = "BNE";
|
||||
10'b1100011_100: name = "BLT";
|
||||
10'b1100011_101: name = "BGE";
|
||||
10'b1100011_110: name = "BLTU";
|
||||
10'b1100011_111: name = "BGEU";
|
||||
10'b1100111_000: name = "JALR";
|
||||
10'b1101111_???: name = "JAL";
|
||||
10'b1110011_000: if (imm == 0) name = "ECALL";
|
||||
else if (imm == 1) name = "EBREAK";
|
||||
else if (imm == 2) name = "URET";
|
||||
else if (imm == 258) name = "SRET";
|
||||
else if (imm == 770) name = "MRET";
|
||||
else name = "ILLEGAL";
|
||||
10'b1110011_001: name = "CSRRW";
|
||||
10'b1110011_010: name = "CSRRS";
|
||||
10'b1110011_011: name = "CSRRC";
|
||||
10'b1110011_101: name = "CSRRWI";
|
||||
10'b1110011_110: name = "CSRRSI";
|
||||
10'b1110011_111: name = "CSRRCI";
|
||||
10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W";
|
||||
else if (funct7[6:2] == 5'b00011) name = "SC.W";
|
||||
else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
|
||||
else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
|
||||
else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
|
||||
else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
|
||||
else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
|
||||
else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
|
||||
else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
|
||||
else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
|
||||
else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
|
||||
else name = "ILLEGAL";
|
||||
10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D";
|
||||
else if (funct7[6:2] == 5'b00011) name = "SC.D";
|
||||
else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
|
||||
else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
|
||||
else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
|
||||
else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
|
||||
else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
|
||||
else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
|
||||
else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
|
||||
else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
|
||||
else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
|
||||
else name = "ILLEGAL";
|
||||
10'b0001111_???: name = "FENCE";
|
||||
default: name = "ILLEGAL";
|
||||
endcase
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user