Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

wally-pipelined/src/ebu/ahblite.sv

@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 package ahbliteState;
-  typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
+  typedef enum logic [3:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
 endpackage
 
 module ahblite (

wally-pipelined/src/ieu/extend.sv

@@ -30,7 +30,7 @@ module extend (
   input  logic [2:0]        ImmSrcD,
   output logic [`XLEN-1:0 ] ExtImmD);
 
-  logic [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
+  localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
  
   generate
     always_comb

wally-pipelined/src/mmu/decoder.sv

@@ -31,6 +31,7 @@ module decoder #(parameter BINARY_BITS = 3) (
 );
 
   // *** Double check whether this synthesizes as expected
+  //     -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists
   assign one_hot = 1 << binary;
 
 endmodule