forked from Github_Repos/cvw
		
	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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						commit
						41a19153cc
					
				@ -348,8 +348,8 @@ module testbench();
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  };
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  string tests64p[] = '{
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    "rv64p/WALLY-MCAUSE", "4000",
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    "rv64p/WALLY-SCAUSE", "3000",
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    "rv64p/WALLY-MCAUSE", "3000",
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    "rv64p/WALLY-SCAUSE", "2000",
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    "rv64p/WALLY-MEPC", "5000",
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    "rv64p/WALLY-SEPC", "4000",
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    "rv64p/WALLY-MTVAL", "6000",
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@ -363,18 +363,18 @@ module testbench();
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  };
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  string tests32p[] = '{
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    // "rv32p/WALLY-MCAUSE", "4000",
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    // "rv32p/WALLY-SCAUSE", "3000",
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    // "rv32p/WALLY-MEPC", "5000",
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    // "rv32p/WALLY-SEPC", "4000",
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    // "rv32p/WALLY-MTVAL", "5000",
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    // "rv32p/WALLY-STVAL", "4000",
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    // "rv32p/WALLY-MARCHID", "4000",
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    // "rv32p/WALLY-MIMPID", "4000",
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    // "rv32p/WALLY-MHARTID", "4000",
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    // "rv32p/WALLY-MVENDORID", "4000"
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    // "rv32p/WALLY-MTVEC", "2000",
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    // "rv32p/WALLY-STVEC", "2000"
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    "rv32p/WALLY-MCAUSE", "3000",
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    "rv32p/WALLY-SCAUSE", "2000",
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    "rv32p/WALLY-MEPC", "5000",
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    "rv32p/WALLY-SEPC", "4000",
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    "rv32p/WALLY-MTVAL", "5000",
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    "rv32p/WALLY-STVAL", "4000",
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    "rv32p/WALLY-MARCHID", "4000",
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    "rv32p/WALLY-MIMPID", "4000",
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    "rv32p/WALLY-MHARTID", "4000",
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    "rv32p/WALLY-MVENDORID", "4000",
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    "rv32p/WALLY-MTVEC", "2000",
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    "rv32p/WALLY-STVEC", "2000"
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  };
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  string tests64periph[] = '{
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@ -423,7 +423,7 @@ module testbench();
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      end
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      //tests = {tests64a, tests};
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      //tests = tests64p;
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      tests = tests64p;
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    end else begin // RV32
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      // *** add the 32 bit bp tests
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      if (TESTSPERIPH) begin 
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@ -437,6 +437,8 @@ module testbench();
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          if (`A_SUPPORTED) tests = {tests, tests32a};
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          if (`MEM_VIRTMEM) tests = {tests, tests32mmu};
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      end
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      //tests = tests32p;
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    end
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  end
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@ -296,7 +296,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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testCount = 16;
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testCount = 8;
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# setup
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# Change this seed to a different constant value for every test
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@ -336,7 +336,15 @@ for xlen in xlens:
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    # insert generic header
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    h = open("../testgen_header.S", "r")
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    for line in h:  
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      f.write(line)
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     f.write(line.replace("RV_COMPLIANCE_RV64M", "RV_COMPLIANCE_RV" + str(xlen) + "M"))
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    # f.write(f"""
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    #   #include "riscv_test_macros.h"
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    #   #include "compliance_test.h"
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    #   #include "compliance_io.h"
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    #   0000000080000000 <_start>:
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    #   80000000: 0480006f            j 80000048 <reset_vector>
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    # """)
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    # We need to leave at least one bit in medeleg unset so that we have a way to get
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    # back to machine mode when the tests are complete (otherwise we'll only ever be able
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@ -383,6 +391,14 @@ for xlen in xlens:
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      lines = f"""
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        add x7, x6, x0
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        csrr x19, mtvec
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        slli  a0,a0,0x1f
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        slli  a0,a0,0x1e
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        slli  a0,a0,0x1d
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        slli  a0,a0,0x1c
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        slli  a0,a0,0x1b
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        slli  a0,a0,0x1a
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        slli  a0,a0,0x19
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      """
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      # Not used — user mode traps are deprecated
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