forked from Github_Repos/cvw
Add tests for sepc register
This commit is contained in:
Domenico Ottolia
parent
0c307d2db1
commit
bf86a809eb
@ -75,6 +75,8 @@ module csrm #(parameter
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DPC = 12'h7B1,
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DSCRATCH0 = 12'h7B2,
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DSCRATCH1 = 12'h7B3,
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// Constants
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ZERO = {(`XLEN){1'b0}},
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ALL_ONES = 32'hfffffff,
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MEDELEG_MASK = ~(ZERO | 1'b1 << 11),
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@ -345,7 +345,8 @@ module testbench();
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"rv64p/WALLY-MCAUSE", "2000",
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"rv64p/WALLY-SCAUSE", "2000",
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"rv64p/WALLY-UCAUSE", "2000",
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"rv64p/WALLY-EPC", "3000",
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"rv64p/WALLY-MEPC", "4000",
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"rv64p/WALLY-SEPC", "4000",
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"rv64p/WALLY-TVAL", "3000",
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"rv64p/WALLY-MARCHID", "4000",
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"rv64p/WALLY-MIMPID", "4000",
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@ -357,7 +358,8 @@ module testbench();
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"rv32p/WALLY-MCAUSE", "2000",
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"rv32p/WALLY-SCAUSE", "2000",
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"rv32p/WALLY-UCAUSE", "2000",
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"rv32p/WALLY-EPC", "3000",
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"rv32p/WALLY-MEPC", "4000",
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"rv32p/WALLY-SEPC", "4000",
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"rv32p/WALLY-TVAL", "3000",
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"rv32p/WALLY-MARCHID", "4000",
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"rv32p/WALLY-MIMPID", "4000",
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@ -425,8 +427,6 @@ module testbench();
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if (`A_SUPPORTED) tests = {tests, tests32a};
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if (`MEM_VIRTMEM) tests = {tests32mmu, tests};
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end
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//tests = tests32p;
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end
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end
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@ -19,6 +19,8 @@ from random import getrandbits
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# functions
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##################################
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#For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
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def randRegs():
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reg1 = randint(1,20)
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reg2 = randint(1,20)
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@ -31,99 +33,54 @@ def randRegs():
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def writeVectors(storecmd):
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global testnum
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# Breakpoint
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# Load address misaligned
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writeTest(storecmd, f, r, f"""
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ebreak
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""")
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ecall
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""", False, 9)
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def writeTest(storecmd, f, r, test, mode = "m", resetHander = ""):
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def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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global testnum
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global testMode
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noprand = ""
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for i in range(0, randint(0, 32)):
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noprand+="nop\n"
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nops = ""
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for i in range(0, randint(1, 16)):
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nops+="nop\n"
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# Setup
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# TODO: Adding 8 to x30 won't work for 32 bit?
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# x31: Old mtvec value
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# x30: trap handler address
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# x29: Old mtvec value for user/supervisor mode
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# x28: Old mstatus value
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# x27: Old mepc value
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# x26: 0 if we should execute mret normally. 1 otherwise. This allows us to stay in machine
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# x25: x24 - x23 should = 0
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# x24: expected mepc value
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# x23: actual mepc value
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lines = f"""
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# Testcase {testnum}
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csrrs x31, mtvec, x0
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auipc x30, 0
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addi x30, x30, 12
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j _jtest{testnum}
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# Machine trap vector
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csrrs x23, mepc, x0
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addi x1, x23, 4
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csrrw x0, mepc, x1
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mret
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# Actual test
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_jtest{testnum}:
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csrrw x0, mtvec, x30
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# Start test code
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li x25, 0x7BAD
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li x23, 0x7BAD
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auipc x24, 0
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{nops}
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li x25, 0xDEADBEA7
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auipc x26, 0
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addi x26, x26, 8
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{test}
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{noprand}
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# Finished test. Reset to old mtvec
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_jend{testnum}:
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addi x24, x24, 4 # x24 should be the address of the test
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sub x25, x24, x23
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csrrw x0, mtvec, x31
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{storecmd} x25, 0(x7)
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addi x7, x7, {wordsize}
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"""
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f.write(lines)
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expected = 0
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#expected = 42
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lines += storecmd + " x25, " + str(wordsize*testnum) + "(x6)\n"
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#lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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# lines += storecmd + " x0" + ", " + str(wordsize*testnum) + "(x6)\n"
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# #lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
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# f.write(lines)
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# if (xlen == 32):
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# line = formatrefstr.format(expected)+"\n"
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# else:
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# line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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# r.write(line)
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# testnum = testnum+1
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##################################
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# main body
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##################################
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# change these to suite your tests
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# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 40; # Doesn't work when numrand = 10
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numrand = 64;
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# setup
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seed(0xC365DDEB9173AB42) # make tests reproducible
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seed(0x9365DDEB9173AB42) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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@ -141,44 +98,164 @@ for xlen in xlens:
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0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
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2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
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]
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-EPC"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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for testMode in ["m", "s"]:
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-" + testMode.upper() + "EPC"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# print directed and random test vectors
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for i in range(0,numrand):
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writeVectors(storecmd)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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# All registers used:
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# x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
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# ...
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# x26: expected epc value
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# x25: value to write to memory
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# ...
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# x19: mtvec old value
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# x18: medeleg old value
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# x17: sedeleg old value
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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lines = f"""
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add x7, x6, x0
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csrr x19, mtvec
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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csrr x18, medeleg
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li x9, {"0b1100000000" if testMode == "s" or testMode == "u" else "0b0000000000"}
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csrs medeleg, x9
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"""
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if testMode == "u":
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lines += f"""
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csrr x17, sedeleg
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li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
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csrs sedeleg, x9
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"""
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lines += f"""
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li x30, 0
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la x1, _j_m_trap
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csrw mtvec, x1
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la x1, _j_s_trap
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csrw stvec, x1
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la x1, _j_u_trap
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csrw utvec, x1
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j _j_t_begin
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_j_m_trap:
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csrrs x1, mepc, x0
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{"sub x25, x26, x1" if testMode == "m" else "li x25, 0xBAD00003"}
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addi x1, x1, 4
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csrrw x0, mepc, x1
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bnez x30, _j_all_end
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mret
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_j_s_trap:
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csrrs x1, sepc, x0
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{"sub x25, x26, x1" if testMode == "s" else "li x25, 0xBAD00001"}
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addi x1, x1, 4
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csrrw x0, sepc, x1
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bnez x30, _j_goto_machine_mode
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sret
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_j_u_trap:
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csrrs x1, uepc, x0
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{"sub x25, x26, x1" if testMode == "u" else "li x25, 0xBAD00000"}
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addi x1, x1, 4
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csrrw x0, uepc, x1
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bnez x30, _j_goto_supervisor_mode
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uret
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_j_goto_supervisor_mode:
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csrw sedeleg, x17
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j _j_goto_machine_mode
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_j_goto_machine_mode:
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csrw medeleg, x18
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li x30, 1
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ecall
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_j_t_begin:
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"""
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fromModeOptions = ["s", "u"] if testMode == "m" else ["u"]
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f.write(lines)
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for fromMode in fromModeOptions:
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lines = ""
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lines += f"""
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li x1, 0b110000000000
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csrrc x28, mstatus, x1
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li x1, 0b0100000000000
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csrrs x28, mstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrw mepc, x1
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mret
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# We're now in supervisor mode...
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"""
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if fromMode == "u":
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lines += f"""
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li x1, 0b110000000000
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csrrc x28, sstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the sret instruction
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csrw sepc, x1
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sret
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# We're now in user mode...
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"""
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# print directed and random test vectors
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f.write(lines)
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for i in range(0,numrand):
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writeVectors(storecmd)
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f.write(f"""
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li x30, 1
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ecall
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_j_all_end:
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csrw mtvec, x19
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""")
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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