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progress on bus and lrsc

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This commit is contained in:
bbracker 2021-04-26 07:43:16 -04:00
parent 27ef10df07
commit 1cc0dcc83f
8 changed files with 50 additions and 43 deletions
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26
wally-pipelined/regression/wave-dos/cache-waves.do
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@ -21,18 +21,6 @@ add wave -hex /testbench/dut/hart/ifu/PCD
add wave -hex /testbench/dut/hart/ifu/InstrD
add wave /testbench/InstrDName
add wave -hex /testbench/dut/hart/ifu/ic/InstrRawD
add wave -hex /testbench/dut/hart/ifu/ic/controller/AlignedInstrRawD
add wave -divider
add wave -hex /testbench/dut/hart/ifu/ic/controller/FetchState
add wave -hex /testbench/dut/hart/ifu/ic/controller/FetchWordNum
add wave -hex /testbench/dut/hart/ifu/ic/controller/ICacheMemWriteEnable
add wave -hex /testbench/dut/hart/ifu/ic/InstrPAdrF
add wave -hex /testbench/dut/hart/ifu/ic/InstrAckF
add wave -hex /testbench/dut/hart/ifu/ic/controller/ICacheMemWriteData
add wave -hex /testbench/dut/hart/ifu/ic/controller/ICacheMemWritePAdr
add wave -hex /testbench/dut/hart/ifu/ic/controller/MisalignedState
add wave -hex /testbench/dut/hart/ifu/ic/controller/MisalignedHalfInstrF
add wave -divider
@ -63,12 +51,15 @@ add wave -hex /testbench/dut/hart/ebu/HTRANS
add wave -hex /testbench/dut/hart/ebu/HRDATA
add wave -hex /testbench/dut/hart/ebu/HWRITE
add wave -hex /testbench/dut/hart/ebu/HWDATA
add wave -hex /testbench/dut/hart/ebu/CaptureDataM
add wave -divider
add wave -hex /testbench/dut/uncore/dtim/*
add wave -hex /testbench/dut/hart/ebu/ReadDataM
add wave -divider
add wave /testbench/dut/hart/ebu/CaptureDataM
add wave /testbench/dut/hart/ebu/CapturedDataAvailable
add wave /testbench/dut/hart/StallW
add wave -hex /testbench/dut/hart/ebu/CapturedData
add wave -hex /testbench/dut/hart/ebu/ReadDataWnext
add wave -hex /testbench/dut/hart/ebu/ReadDataW
add wave -hex /testbench/dut/hart/ifu/PCW
add wave -hex /testbench/dut/hart/ifu/InstrW
add wave /testbench/InstrWName
@ -78,7 +69,8 @@ add wave -hex /testbench/dut/hart/ieu/dp/ResultW
add wave -hex /testbench/dut/hart/ieu/dp/RdW
add wave -divider
add wave -hex /testbench/dut/uncore/dtim/*
add wave -hex /testbench/dut/hart/dmem/*
add wave -hex /testbench/dut/hart/dmem/genblk1/*
add wave -divider
add wave -hex -r /testbench/*

4
wally-pipelined/src/dmem/dmem.sv
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@ -122,8 +122,8 @@ module dmem (
else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
else ReservationValidM = ReservationValidW; // otherwise don't change valid
end
flopenrc #(`XLEN-2) resadrreg(clk, reset, FlushW, ~StallW && lrM, MemPAdrM[`XLEN-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenrc #(1) resvldreg(clk, reset, FlushW, ~StallW, ReservationValidM, ReservationValidW);
flopenrc #(`XLEN-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`XLEN-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
flopenrc #(1) squashreg(clk, reset, FlushW, ~StallW, SquashSCM, SquashSCW);
end else begin // Atomic operations not supported
assign SquashSCM = 0;

31
wally-pipelined/src/ebu/ahblite.sv
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@ -86,9 +86,9 @@ module ahblite (
logic GrantData;
logic [31:0] AccessAddress;
logic [2:0] AccessSize, PTESize, ISize;
logic [`AHBW-1:0] HRDATAMasked, ReadDataM, ReadDataNewW, ReadDataOldW, WriteData;
logic [`AHBW-1:0] HRDATAMasked, ReadDataM, CapturedData, ReadDataWnext, WriteData;
logic IReady, DReady;
logic CaptureDataM;
logic CaptureDataM,CapturedDataAvailable;
// Describes type of access
logic Atomic, Execute, Write, Read;
@ -192,15 +192,26 @@ module ahblite (
((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD)) || ((BusState == ATOMICWRITE) && (NextBusState != ATOMICWRITE));
assign MMUReadPTE = HRDATA;
assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
// Carefully decide when to update ReadDataW
// ReadDataMstored holds the most recent memory read.
// We need to wait until the pipeline actually advances before we can update the contents of ReadDataW
// (or else the W stage will accidentally get the M stage's data when the pipeline does advance).
assign CaptureDataM = ((BusState == MEMREAD) && (NextBusState != MEMREAD)) ||
((BusState == ATOMICREAD) && (NextBusState == ATOMICWRITE));
// We think this introduces an unnecessary cycle of latency in memory accesses
// *** can the following be simplified down to one register?
// *** examine more closely over summer?
flopenr #(`XLEN) ReadDataNewWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataNewW);
flopenr #(`XLEN) ReadDataOldWReg(clk, reset, CaptureDataM, ReadDataNewW, ReadDataOldW);
assign ReadDataW = (BusState == INSTRREADC) ? ReadDataOldW : ReadDataNewW;
//assign ReadDataW = (BusState == INSTRREADC) ? ReadDataOldW : ReadDataNewW;
((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD));
flopenr #(`XLEN) ReadDataNewWReg(clk, reset, CaptureDataM, ReadDataM, CapturedData);
always @(posedge HCLK, negedge HRESETn)
if (~HRESETn)
CapturedDataAvailable <= #1 1'b0;
else
CapturedDataAvailable <= #1 (StallW) ? (CaptureDataM | CapturedDataAvailable) : 1'b0;
always_comb
casez({StallW && (BusState != ATOMICREAD),CapturedDataAvailable})
2'b00: ReadDataWnext = ReadDataM;
2'b01: ReadDataWnext = CapturedData;
2'b1?: ReadDataWnext = ReadDataW;
endcase
flopr #(`XLEN) ReadDataOldWReg(clk, reset, ReadDataWnext, ReadDataW);
// Extract and sign-extend subwords if necessary
subwordread swr(.*);

3
wally-pipelined/src/ebu/pmachecker.sv
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@ -29,9 +29,8 @@
module pmachecker (
input logic [31:0] HADDR,
input logic HSIZE,
input logic [2:0] HSIZE, HBURST,
input logic HWRITE,
input logic HBURST,
input logic Atomic, Execute, Write, Read,

2
wally-pipelined/src/ifu/icache.sv
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@ -63,7 +63,7 @@ module icache(
logic [`XLEN-1:0] ICacheMemWritePAdr;
logic EndFetchState;
// Output signals from cache memory
logic [`XLEN-1:0] ICacheMemReadData;
logic [31:0] ICacheMemReadData;
logic ICacheMemReadValid;
logic ICacheReadEn;

3
wally-pipelined/src/ifu/ifu.sv
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@ -77,7 +77,8 @@ module ifu (
logic CompressedF;
logic [31:0] InstrRawD, InstrE, InstrW;
localparam [31:0] nop = 32'h00000013; // instruction for NOP
logic reset_q; // *** look at this later.
logic reset_q; // *** look at this later.
logic [`XLEN-1:0] PCPF;
tlb #(.ENTRY_BITS(3), .ITLB(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF),
.PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),

3
wally-pipelined/src/privileged/privileged.sv
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@ -56,7 +56,8 @@ module privileged (
// PMA checker signals
input logic [31:0] HADDR,
input logic HSIZE, HWRITE, HBURST,
input logic HWRITE,
input logic [2:0] HSIZE, HBURST,
input logic Atomic, Execute, Write, Read,
output logic Cacheable, Idempotent, AtomicAllowed,
output logic SquashAHBAccess,

21
wally-pipelined/testbench/testbench-busybear.sv
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@ -1,5 +1,9 @@
`include "wally-config.vh"
package ahbliteState;
typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
endpackage
module testbench_busybear();
logic clk, reset;
@ -504,11 +508,11 @@ module testbench_busybear();
// Track names of instructions
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW;
instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName);
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
instrTrackerTB it(clk, reset,
dut.hart.ifu.icache.controller.FinalInstrRawF,
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
dut.hart.ifu.InstrM, InstrW,
InstrDName, InstrEName, InstrMName, InstrWName);
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// generate clock to sequence tests
always
@ -518,15 +522,14 @@ module testbench_busybear();
endmodule
module instrTrackerTB(
input logic clk, reset, FlushE,
input logic [31:0] InstrD,
input logic [31:0] InstrE, InstrM,
output logic [31:0] InstrW,
output string InstrDName, InstrEName, InstrMName, InstrWName);
input logic clk, reset,
input logic [31:0] InstrF,InstrD,InstrE,InstrM,InstrW,
output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// stage Instr to Writeback for visualization
//flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
instrNameDecTB fdec(InstrF, InstrFName);
instrNameDecTB ddec(InstrD, InstrDName);
instrNameDecTB edec(InstrE, InstrEName);
instrNameDecTB mdec(InstrM, InstrMName);