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Restored to working multiplier after Lab 2

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This commit is contained in:
David Harris 2021-02-25 15:32:43 -05:00
commit a16fd95eed
4 changed files with 189 additions and 3 deletions
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102
wally-pipelined/ppa/ppa.sv Normal file
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@ -0,0 +1,102 @@
// ppa.sv
// Teo Ene & David_Harris@hmc.edu 25 Feb 2021
// Measure PPA of various building blocks
// replace this with the tools setting a library path to a config/skl130 directory containing config.vh
`define LIB SKL130
module top(
input logic a1,
input logic [7:0] a8, b8,
input logic [15:0] a16, b16,
input logic [31:0] a32, b32,
input logic [63:0] a64, b64,
output logic yinv,
output logic [63:0] y1, y2, y3, y4
);
// fo4 inverter
myinv myinv(a1, yinv);)
// adders
add #(8) add8(a8, b8, yadd8);
add #(16) add16(a16, b16, yadd16);
add #(32) add32(a32, b32, yadd32);
add #(64) add64(a64, b64, yadd64);
// mux2, mux3, mux4 of 1, 8, 16, 32, 64
endmodule
module myinv(input a, output y);
driver #(1) drive(a, in1);
assign out = ~in;
load #(1) load(out, y);
endmodule
module add #(parameter WIDTH=8) (
input logic [7:0] a, b,
output logic [7:0] y
);
logic [WIDTH-1:0] in1, in2, out;
driver #(WIDTH) drive1(a, in1);
driver #(WIDTH) drive2(b, in2);
assign out = in1 + in2;
load #(WIDTH) load(out, y);
endmodule
module INVX2(input logic a, output logic y);
generate
if (LIB == SKL130)
sky130_osu_sc_12T_ms__inv_2 inv(a, y);
else if (LIB == SKL90)
scc9gena_inv_2 inv(a, y)
else if (LIB == GF14)
INV_X2N_A10P5PP84TSL_C14(a, y)
endgenerate
endmodule
module driver #(parameter WDITH=1) (
input [WIDTH-1:0] logic a,
output [WIDTH-1:0] logic y
);
logic [WIDTH-1:0] ab;
INVX2 i1[WIDTH-1:0](a, ab);
INVX2 i2[WIDTH-1:0](ab, y);
endmodule
module inv4(input logic a, output logic y);
logic [3:0] b
INVX2 i0(a, b[0]);
INVX2 i1(a, b[1]);
INVX2 i2(a, b[2]);
INVX2 i3(a, b[3]);
INVX2 i00(b[0], y;
INVX2 i01(b[0], y);
INVX2 i02(b[0], y);
INVX2 i03(b[0], y);
INVX2 i10(b[1], y;
INVX2 i11(b[1], y);
INVX2 i12(b[1], y);
INVX2 i13(b[1], y);
INVX2 i20(b[2], y;
INVX2 i21(b[2], y);
INVX2 i22(b[2], y);
INVX2 i23(b[2], y);
INVX2 i30(b[3], y;
INVX2 i31(b[3], y);
INVX2 i32(b[3], y);
INVX2 i33(b[3], y);
endmodule
module load #(parameter WDITH=1) (
input [WIDTH-1:0] logic a,
output [WIDTH-1:0] logic y
);
logic [WIDTH-1:0] ab;
inv4 load[WIDTH-1:0](a, y);
endmodule

4
wally-pipelined/src/ieu/controller.sv
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@ -94,10 +94,14 @@ module controller(
7'b0100011: ControlsD = 21'b0_001_01_01_000_0_00_0_0_0_0_0_0_0; // sw
7'b0110011: if (Funct7D == 7'b0000000 || Funct7D == 7'b0100000)
ControlsD = 21'b1_000_00_00_000_0_10_0_0_0_0_0_0_0; // R-type
else if (Funct7D == 7'b0000001 && `M_SUPPORTED)
ControlsD = 21'b1_000_00_00_100_0_00_0_0_0_0_0_1_0; // Multiply/Divide
else
ControlsD = 21'b0_000_00_00_000_0_00_0_0_0_0_0_0_1; // non-implemented instruction
7'b0111011: if ((Funct7D == 7'b0000000 || Funct7D == 7'b0100000) && `XLEN == 64)
ControlsD = 21'b1_000_00_00_000_0_10_0_0_1_0_0_0_0; // R-type W instructions for RV64i
else if (Funct7D == 7'b0000001 && `M_SUPPORTED && `XLEN == 64)
ControlsD = 21'b1_000_00_00_100_0_00_0_0_1_0_0_1_0; // W-type Multiply/Divide
else
ControlsD = 21'b0_000_00_00_000_0_00_0_0_0_0_0_0_1; // non-implemented instruction
7'b1100011: ControlsD = 21'b0_010_00_00_000_1_01_0_0_0_0_0_0_0; // beq

77
wally-pipelined/src/muldiv/mul.sv Normal file
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@ -0,0 +1,77 @@
///////////////////////////////////////////
// mul.sv
//
// Written: David_Harris@hmc.edu 16 February 2021
// Modified:
//
// Purpose: Multiply instructions
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module mul (
// Execute Stage interface
input logic [`XLEN-1:0] SrcAE, SrcBE,
input logic [2:0] Funct3E,
output logic [`XLEN*2-1:0] ProdE
);
// Number systems
// Let A' = sum(i=0, XLEN-2, A[i]*2^i)
// Unsigned: A = A' + A[XLEN-1]*2^(XLEN-1)
// Signed: A = A' - A[XLEN-1]*2^(XLEN-1)
// Multiplication: A*B
// Let P' = A' * B'
// PA = (A' * B[XLEN-1])
// PB = (B' * A[XLEN-1])
// PP = A[XLEN-1] * B[XLEN-1]
// Signed * Signed = P' + (-PA - PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
// Signed * Unsigned = P' + ( PA - PB)*2^(XLEN-1) - PP*2^(2XLEN-2)
// Unsigned * Unsigned = P' + ( PA + PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
logic [`XLEN*2-1:0] PP1, PP2, PP3, PP4;
logic [`XLEN*2-1:0] Pprime;
logic [`XLEN-2:0] PA, PB;
logic PP;
logic MULH, MULHSU, MULHU;
// portions of product
assign Pprime = {1'b0, SrcAE[`XLEN-2:0]} * {1'b0, SrcBE[`XLEN-2:0]};
assign PA = {(`XLEN-1){SrcAE[`XLEN-1]}} & SrcBE[`XLEN-2:0];
assign PB = {(`XLEN-1){SrcBE[`XLEN-1]}} & SrcAE[`XLEN-2:0];
assign PP = SrcAE[`XLEN-1] & SrcBE[`XLEN-1];
// flavor of multiplication
assign MULH = (Funct3E == 2'b01);
assign MULHSU = (Funct3E == 2'b10);
assign MULHU = (Funct3E == 2'b11);
// Handle signs
assign PP1 = Pprime; // same for all flavors
assign PP2 = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}};
assign PP3 = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}};
always_comb
if (MULH) PP4 = {1'b1, PP, {(`XLEN-3){1'b0}}, 1'b1, {(`XLEN){1'b0}}};
else if (MULHSU) PP4 = {1'b1, ~PP, {(`XLEN-2){1'b0}}, 1'b1, {(`XLEN-1){1'b0}}};
else PP4 = {1'b0, PP, {(`XLEN*2-2){1'b0}}};
assign ProdE = PP1 + PP2 + PP3 + PP4; //SrcAE * SrcBE;
endmodule

9
wally-pipelined/src/muldiv/muldiv.sv
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@ -36,7 +36,7 @@ module muldiv (
// Writeback stage
output logic [`XLEN-1:0] MulDivResultW,
// hazards
input logic FlushM, FlushW
input logic StallM, StallW, FlushM, FlushW
);
generate
@ -46,6 +46,9 @@ module muldiv (
logic [`XLEN-1:0] QuotE, RemE;
logic [`XLEN*2-1:0] ProdE;
// Multiplier
mul mul(.*);
// Select result
always_comb
case (Funct3E)
@ -66,8 +69,8 @@ module muldiv (
assign MulDivResultE = PrelimResultE;
end
floprc #(`XLEN) MulDivResultMReg(clk, reset, FlushM, MulDivResultE, MulDivResultM);
floprc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, MulDivResultM, MulDivResultW);
flopenrc #(`XLEN) MulDivResultMReg(clk, reset, FlushM, ~StallM, MulDivResultE, MulDivResultM);
flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW);
end else begin // no M instructions supported
assign MulDivResultW = 0;
end