forked from Github_Repos/cvw
Merge branch 'main' into cache
Conflicts: wally-pipelined/regression/wave-dos/ahb-waves.do wally-pipelined/src/ifu/ifu.sv wally-pipelined/testbench/testbench-busybear.sv wally-pipelined/testbench/testbench-imperas.sv
This commit is contained in:
Jarred Allen
commit
7ca57cc4fc
@ -138,7 +138,7 @@ add wave /testbench_busybear/InstrMName
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#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM
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#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM
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#add wave -divider
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add wave -hex /testbench_busybear/dut/hart/ifu/PCW
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add wave -hex /testbench_busybear/PCW
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW
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add wave /testbench_busybear/InstrWName
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#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW
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@ -69,8 +69,8 @@ add wave -hex /testbench/dut/hart/ifu/PCM
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add wave -hex /testbench/dut/hart/ifu/InstrM
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add wave /testbench/InstrMName
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add wave -divider Write
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add wave -hex /testbench/dut/hart/ifu/PCW
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add wave -hex /testbench/dut/hart/ifu/InstrW
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add wave -hex /testbench/PCW
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add wave -hex /testbench/InstrW
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add wave /testbench/InstrWName
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#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
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#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
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@ -81,7 +81,7 @@ add wave -divider Regfile_signals
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#add wave -hex /testbench/dut/uncore/HADDR
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#add wave -hex /testbench/dut/uncore/HWDATA
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#add wave -divider
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#add wave -hex /testbench/dut/hart/ifu/PCW
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#add wave -hex /testbench/PCW
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#add wave /testbench/InstrWName
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#add wave /testbench/dut/hart/ieu/dp/RegWriteW
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#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
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@ -69,8 +69,8 @@ add wave -hex /testbench/dut/hart/ifu/PCM
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add wave -hex /testbench/dut/hart/ifu/InstrM
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add wave /testbench/InstrMName
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add wave -divider Write
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add wave -hex /testbench/dut/hart/ifu/PCW
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add wave -hex /testbench/dut/hart/ifu/InstrW
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add wave -hex /testbench/PCW
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add wave -hex /testbench/InstrW
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add wave /testbench/InstrWName
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#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
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#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
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@ -81,7 +81,7 @@ add wave -divider Regfile_signals
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#add wave -hex /testbench/dut/uncore/HADDR
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#add wave -hex /testbench/dut/uncore/HWDATA
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#add wave -divider
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#add wave -hex /testbench/dut/hart/ifu/PCW
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#add wave -hex /testbench/PCW
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#add wave /testbench/InstrWName
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#add wave /testbench/dut/hart/ieu/dp/RegWriteW
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#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
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@ -45,7 +45,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite
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add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR
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add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATA
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add wave -noupdate -divider <NULL>
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCW
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add wave -noupdate -radix hexadecimal /testbench/PCW
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add wave -noupdate /testbench/InstrWName
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add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
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@ -219,7 +219,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/IllegalCompInstrD
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPlusUpperF
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCD
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCW
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add wave -noupdate -radix hexadecimal /testbench/PCW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkD
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkE
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkM
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@ -44,8 +44,8 @@ add wave /testbench/dut/uncore/dtim/memwrite
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add wave -hex /testbench/dut/uncore/HADDR
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add wave -hex /testbench/dut/uncore/HWDATA
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add wave -divider
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add wave -hex /testbench/dut/hart/ifu/PCW
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add wave -hex /testbench/dut/hart/ifu/InstrW
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add wave -hex /testbench/PCW
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add wave -hex /testbench/InstrW
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add wave /testbench/InstrWName
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add wave /testbench/dut/hart/ieu/dp/RegWriteW
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add wave -hex /testbench/dut/hart/ieu/dp/ResultW
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@ -125,7 +125,7 @@ add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCW
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr
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add wave -noupdate -group {function radix debug} -radix unsigned /testbench/functionRadix/function_radix/ProgramAddrIndex
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/reset
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@ -192,10 +192,10 @@ module ifu (
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flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE);
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flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM);
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flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later
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// flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later
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flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
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flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later
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// flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later
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flopenrc #(4) InstrClassRegE(.clk(clk),
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.reset(reset),
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@ -143,6 +143,9 @@ module testbench_busybear();
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logic [63:0] pcExpected;
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logic [63:0] regExpected;
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integer regNumExpected;
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logic [`XLEN-1:0] PCW;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
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genvar i;
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generate
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@ -349,8 +352,8 @@ module testbench_busybear();
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string PCtextW, PCtext2W;
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logic [31:0] InstrWExpected;
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logic [63:0] PCWExpected;
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always @(dut.hart.ifu.PCW or dut.hart.ieu.InstrValidW) begin
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if(dut.hart.ieu.InstrValidW && dut.hart.ifu.PCW != 0) begin
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always @(PCW or dut.hart.ieu.InstrValidW) begin
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if(dut.hart.ieu.InstrValidW && PCW != 0) begin
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if($feof(data_file_PCW)) begin
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$display("no more PC data to read");
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`ERROR
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@ -363,8 +366,8 @@ module testbench_busybear();
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scan_file_PCW = $fscanf(data_file_PCW, "%x\n", InstrWExpected);
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// then expected PC value
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scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
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if(~equal(dut.hart.ifu.PCW,PCWExpected,2)) begin
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$display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.hart.ifu.PCW, PCWExpected);
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if(~equal(PCW,PCWExpected,2)) begin
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$display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, PCW, PCWExpected);
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`ERROR
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end
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//if(it.InstrW != InstrWExpected) begin
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@ -481,6 +484,7 @@ module testbench_busybear();
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// Track names of instructions
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
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instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName);
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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@ -494,3 +498,128 @@ module testbench_busybear();
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end
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endmodule
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module instrTrackerTB(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrD,
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input logic [31:0] InstrE, InstrM,
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output logic [31:0] InstrW,
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output string InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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//flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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instrNameDecTB wdec(InstrW, InstrWName);
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endmodule
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// decode the instruction name, to help the test bench
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module instrNameDecTB(
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input logic [31:0] instr,
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output string name);
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logic [6:0] op;
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logic [2:0] funct3;
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logic [6:0] funct7;
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logic [11:0] imm;
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assign op = instr[6:0];
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assign funct3 = instr[14:12];
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assign funct7 = instr[31:25];
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assign imm = instr[31:20];
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// it would be nice to add the operands to the name
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// create another variable called decoded
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always_comb
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casez({op, funct3})
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10'b0000000_000: name = "BAD";
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10'b0000011_000: name = "LB";
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10'b0000011_001: name = "LH";
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10'b0000011_010: name = "LW";
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10'b0000011_011: name = "LD";
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10'b0000011_100: name = "LBU";
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10'b0000011_101: name = "LHU";
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10'b0000011_110: name = "LWU";
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10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
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else name = "ADDI";
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10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
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else name = "ILLEGAL";
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10'b0010011_010: name = "SLTI";
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10'b0010011_011: name = "SLTIU";
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10'b0010011_100: name = "XORI";
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10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
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else if (funct7[6:1] == 6'b010000) name = "SRAI";
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else name = "ILLEGAL";
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10'b0010011_110: name = "ORI";
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10'b0010011_111: name = "ANDI";
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10'b0010111_???: name = "AUIPC";
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10'b0100011_000: name = "SB";
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10'b0100011_001: name = "SH";
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10'b0100011_010: name = "SW";
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10'b0100011_011: name = "SD";
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10'b0011011_000: name = "ADDIW";
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10'b0011011_001: name = "SLLIW";
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10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
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else if (funct7 == 7'b0100000) name = "SRAIW";
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else name = "ILLEGAL";
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10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
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else if (funct7 == 7'b0100000) name = "SUBW";
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else name = "ILLEGAL";
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10'b0111011_001: name = "SLLW";
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10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
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else if (funct7 == 7'b0100000) name = "SRAW";
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else name = "ILLEGAL";
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10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
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else if (funct7 == 7'b0000001) name = "MUL";
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else if (funct7 == 7'b0100000) name = "SUB";
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else name = "ILLEGAL";
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10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
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else if (funct7 == 7'b0000001) name = "MULH";
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else name = "ILLEGAL";
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10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
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else if (funct7 == 7'b0000001) name = "MULHSU";
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else name = "ILLEGAL";
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10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
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else if (funct7 == 7'b0000001) name = "DIV";
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else name = "ILLEGAL";
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10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
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else if (funct7 == 7'b0000001) name = "MUL";
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else name = "ILLEGAL";
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10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
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else if (funct7 == 7'b0000001) name = "DIVU";
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else if (funct7 == 7'b0100000) name = "SRA";
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else name = "ILLEGAL";
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10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
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else if (funct7 == 7'b0000001) name = "REM";
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else name = "ILLEGAL";
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10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
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else if (funct7 == 7'b0000001) name = "REMU";
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else name = "ILLEGAL";
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10'b0110111_???: name = "LUI";
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10'b1100011_000: name = "BEQ";
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10'b1100011_001: name = "BNE";
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10'b1100011_100: name = "BLT";
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10'b1100011_101: name = "BGE";
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10'b1100011_110: name = "BLTU";
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10'b1100011_111: name = "BGEU";
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10'b1100111_000: name = "JALR";
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10'b1101111_???: name = "JAL";
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10'b1110011_000: if (imm == 0) name = "ECALL";
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else if (imm == 1) name = "EBREAK";
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else if (imm == 2) name = "URET";
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else if (imm == 258) name = "SRET";
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else if (imm == 770) name = "MRET";
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else name = "ILLEGAL";
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10'b1110011_001: name = "CSRRW";
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10'b1110011_010: name = "CSRRS";
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10'b1110011_011: name = "CSRRC";
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10'b1110011_101: name = "CSRRWI";
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10'b1110011_110: name = "CSRRSI";
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10'b1110011_111: name = "CSRRCI";
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10'b0001111_???: name = "FENCE";
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default: name = "ILLEGAL";
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endcase
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endmodule
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@ -60,12 +60,18 @@ module testbench();
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||||
assign HRDATAEXT = 0;
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wallypipelinedsoc dut(.*);
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// Track names of instructions
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logic [31:0] InstrW;
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flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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||||
dut.hart.ifu.InstrF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
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||||
dut.hart.ifu.InstrM, InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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||||
// initialize tests
|
||||
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||||
logic [`XLEN-1:0] PCW;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
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||||
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||||
integer j;
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||||
initial
|
||||
begin
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||||
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||||
@ -59,12 +59,20 @@ module testbench();
|
||||
assign HRESPEXT = 0;
|
||||
assign HRDATAEXT = 0;
|
||||
wallypipelinedsoc dut(.*);
|
||||
|
||||
logic [31:0] InstrW;
|
||||
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
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||||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.InstrF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
logic [`XLEN-1:0] PCW;
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||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
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||||
|
||||
// initialize tests
|
||||
integer j;
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||||
initial
|
||||
|
||||
@ -38,7 +38,7 @@ module testbench();
|
||||
logic [`XLEN-1:0] signature[0:10000];
|
||||
logic [`XLEN-1:0] testadr;
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
//logic [31:0] InstrW;
|
||||
logic [31:0] InstrW;
|
||||
logic [`XLEN-1:0] meminit;
|
||||
string tests64a[] = '{
|
||||
"rv64a/WALLY-AMO", "2110",
|
||||
@ -331,8 +331,10 @@ string tests32i[] = {
|
||||
logic [1:0] HTRANS;
|
||||
logic HMASTLOCK;
|
||||
logic HCLK, HRESETn;
|
||||
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
|
||||
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
|
||||
// pick tests based on modes supported
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||||
initial
|
||||
if (`XLEN == 64) begin // RV64
|
||||
@ -371,8 +373,8 @@ string tests32i[] = {
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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||||
dut.hart.ifu.ic.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName,
|
||||
InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// initialize tests
|
||||
initial
|
||||
|
||||
@ -73,13 +73,15 @@ module testbench();
|
||||
assign HRDATAEXT = 0;
|
||||
|
||||
wallypipelinedsoc dut(.*);
|
||||
|
||||
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
logic [`XLEN-1:0] PCW;
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
|
||||
// initialize tests
|
||||
initial
|
||||
begin
|
||||
@ -187,7 +189,7 @@ module instrTrackerTB(
|
||||
output string InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// stage Instr to Writeback for visualization
|
||||
flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
|
||||
//flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
|
||||
|
||||
instrNameDecTB ddec(InstrD, InstrDName);
|
||||
instrNameDecTB edec(InstrE, InstrEName);
|
||||
|
||||
@ -92,13 +92,15 @@ module testbench();
|
||||
assign HRDATAEXT = 0;
|
||||
|
||||
wallypipelinedsoc dut(.*);
|
||||
|
||||
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
|
||||
// Track names of instructions
|
||||
instrTrackerTBPriv it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
logic [`XLEN-1:0] PCW;
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
|
||||
// initialize tests
|
||||
initial
|
||||
begin
|
||||
@ -226,7 +228,8 @@ module instrTrackerTBPriv(
|
||||
output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// stage Instr to Writeback for visualization
|
||||
// flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
|
||||
//flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
|
||||
|
||||
|
||||
instrNameDecTB fdec(InstrF, InstrFName);
|
||||
instrNameDecTB ddec(InstrD, InstrDName);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user