forked from Github_Repos/cvw
Refactor TLB into multiple files
This commit is contained in:
Thomas Fleming
parent
c54aecde73
commit
fc39535e4e
@ -50,7 +50,6 @@
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/* *** TODO:
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* - add LRU algorithm (select the write index based on which entry was used
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* least recently)
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* - refactor modules into multiple files
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*/
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// The TLB will have 2**ENTRY_BITS total entries
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@ -96,10 +95,8 @@ module tlb #(parameter ENTRY_BITS = 3) (
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assign SvMode = SATP_REGW[63]; // currently just a boolean whether translation enabled
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end
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endgenerate
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// *** Currently fake virtual memory being on for testing purposes
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// *** DO NOT ENABLE UNLESS TESTING
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// assign SvMode = 1;
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// Whether translation should occur
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assign Translate = SvMode & (PrivilegeModeW != `M_MODE);
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// *** If we want to support multiple virtual memory modes (ie sv39 AND sv48),
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@ -113,18 +110,18 @@ module tlb #(parameter ENTRY_BITS = 3) (
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// Sections of the virtual and physical addresses
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logic [`VPN_BITS-1:0] VirtualPageNumber;
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logic [`PPN_BITS-1:0] PhysicalPageNumber, PhysicalPageNumberMixed;
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logic [`PA_BITS-1:0] PhysicalAddressFull;
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// Sections of the page table entry
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logic [7:0] PTEAccessBits;
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logic [11:0] PageOffset;
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logic [`PA_BITS-1:0] PhysicalAddressFull;
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// Pattern location in the CAM and type of page hit
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logic [ENTRY_BITS-1:0] VPNIndex;
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logic [1:0] HitPageType;
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// RAM access location
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logic [ENTRY_BITS-1:0] EntryIndex;
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logic CAMHit;
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// Whether the virtual address has a match in the CAM
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logic CAMHit;
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assign VirtualPageNumber = VirtualAddress[`VPN_BITS+11:12];
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assign PageOffset = VirtualAddress[11:0];
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@ -138,17 +135,26 @@ module tlb #(parameter ENTRY_BITS = 3) (
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// *** check whether access is allowed, otherwise fault
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assign TLBPageFault = 0; // *** temporary
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// *** Not the cleanest solution.
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// The highest segment of the physical page number has some extra bits
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// than the highest segment of the virtual page number.
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localparam EXTRA_PHYSICAL_BITS = `PPN_HIGH_SEGMENT_BITS - `VPN_SEGMENT_BITS;
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// Replace segments of the virtual page number with segments of the physical
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// page number. For 4 KB pages, the entire virtual page number is replaced.
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// For superpages, some segments are considered offsets into a larger page.
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page_number_mixer #(`PPN_BITS, `PPN_HIGH_SEGMENT_BITS)
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physical_mixer(PhysicalPageNumber,
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{{EXTRA_PHYSICAL_BITS{1'b0}}, VirtualPageNumber},
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HitPageType,
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PhysicalPageNumberMixed);
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// Provide physical address only on TLBHits to cause catastrophic errors if
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// garbage address is used.
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assign PhysicalAddressFull = (TLBHit) ?
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{PhysicalPageNumberMixed, PageOffset} : '0;
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// Output the hit physical address if translation is currently on.
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generate
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if (`XLEN == 32) begin
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mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], Translate, PhysicalAddress);
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@ -160,92 +166,3 @@ module tlb #(parameter ENTRY_BITS = 3) (
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assign TLBHit = CAMHit & TLBAccess;
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assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess;
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endmodule
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// *** use actual flop notation instead of initialbegin and alwaysff
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module tlb_ram #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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input [ENTRY_BITS-1:0] VPNIndex, // Index to read from
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input [ENTRY_BITS-1:0] WriteIndex,
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input [`XLEN-1:0] PageTableEntryWrite,
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input TLBWrite,
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output [`PPN_BITS-1:0] PhysicalPageNumber,
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output [7:0] PTEAccessBits
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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logic [`XLEN-1:0] ram [0:NENTRIES-1];
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logic [`XLEN-1:0] PageTableEntry;
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always @(posedge clk) begin
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if (TLBWrite) ram[WriteIndex] <= PageTableEntryWrite;
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end
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assign PageTableEntry = ram[VPNIndex];
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assign PTEAccessBits = PageTableEntry[7:0];
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assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10];
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initial begin
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for (int i = 0; i < NENTRIES; i++)
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ram[i] = `XLEN'b0;
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end
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endmodule
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module tlb_cam #(parameter ENTRY_BITS = 3,
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parameter KEY_BITS = 20,
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parameter HIGH_SEGMENT_BITS = 10) (
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input clk, reset,
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input [KEY_BITS-1:0] VirtualPageNumber,
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input [1:0] PageTypeWrite,
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input [ENTRY_BITS-1:0] WriteIndex,
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input TLBWrite,
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input TLBFlush,
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output [ENTRY_BITS-1:0] VPNIndex,
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output [1:0] HitPageType,
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output CAMHit
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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logic [NENTRIES-1:0] CAMLineWrite;
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logic [1:0] PageTypeList [0:NENTRIES-1];
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logic [NENTRIES-1:0] Matches;
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// Determine which CAM line should be written, based on a binary index
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decoder #(ENTRY_BITS) decoder(WriteIndex, CAMLineWrite);
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// Create NENTRIES CAM lines, each of which will independently consider
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// whether the requested virtual address is a match. Each line stores the
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// original virtual page number from when the address was written, regardless
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// of page type. However, matches are determined based on a subset of the
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// page number segments.
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generate
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genvar i;
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for (i = 0; i < NENTRIES; i++) begin
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cam_line #(KEY_BITS, HIGH_SEGMENT_BITS) cam_line(
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.CAMLineWrite(CAMLineWrite[i] && TLBWrite),
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.PageType(PageTypeList[i]),
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.Match(Matches[i]),
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.*);
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end
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endgenerate
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// In case there are multiple matches in the CAM, select only one
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priority_encoder #(ENTRY_BITS) match_priority(Matches, VPNIndex);
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assign CAMHit = |Matches & ~TLBFlush;
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assign HitPageType = PageTypeList[VPNIndex];
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endmodule
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module tlb_rand #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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output [ENTRY_BITS-1:0] WriteIndex
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);
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logic [31:0] data;
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assign data = $urandom;
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assign WriteIndex = data[ENTRY_BITS-1:0];
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endmodule
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72
wally-pipelined/src/mmu/tlb_cam.sv
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72
wally-pipelined/src/mmu/tlb_cam.sv
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@ -0,0 +1,72 @@
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///////////////////////////////////////////
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// tlb_cam.sv
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//
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// Written: jtorrey@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Stores virtual page numbers with cached translations.
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// Determines whether a given virtual page number is in the TLB.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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module tlb_cam #(parameter ENTRY_BITS = 3,
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parameter KEY_BITS = 20,
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parameter HIGH_SEGMENT_BITS = 10) (
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input clk, reset,
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input [KEY_BITS-1:0] VirtualPageNumber,
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input [1:0] PageTypeWrite,
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input [ENTRY_BITS-1:0] WriteIndex,
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input TLBWrite,
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input TLBFlush,
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output [ENTRY_BITS-1:0] VPNIndex,
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output [1:0] HitPageType,
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output CAMHit
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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logic [NENTRIES-1:0] CAMLineWrite;
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logic [1:0] PageTypeList [0:NENTRIES-1];
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logic [NENTRIES-1:0] Matches;
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// Determine which CAM line should be written, based on a binary index
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decoder #(ENTRY_BITS) decoder(WriteIndex, CAMLineWrite);
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// Create NENTRIES CAM lines, each of which will independently consider
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// whether the requested virtual address is a match. Each line stores the
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// original virtual page number from when the address was written, regardless
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// of page type. However, matches are determined based on a subset of the
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// page number segments.
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generate
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genvar i;
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for (i = 0; i < NENTRIES; i++) begin
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cam_line #(KEY_BITS, HIGH_SEGMENT_BITS) cam_line(
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.CAMLineWrite(CAMLineWrite[i] && TLBWrite),
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.PageType(PageTypeList[i]),
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.Match(Matches[i]),
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.*);
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end
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endgenerate
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// In case there are multiple matches in the CAM, select only one
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priority_encoder #(ENTRY_BITS) match_priority(Matches, VPNIndex);
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assign CAMHit = |Matches & ~TLBFlush;
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assign HitPageType = PageTypeList[VPNIndex];
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endmodule
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60
wally-pipelined/src/mmu/tlb_ram.sv
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60
wally-pipelined/src/mmu/tlb_ram.sv
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@ -0,0 +1,60 @@
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///////////////////////////////////////////
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// tlb_ram.sv
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//
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// Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Stores page table entries of cached address translations.
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// Outputs the physical page number and access bits of the current
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// virtual address on a TLB hit.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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`include "wally-constants.vh"
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// *** use actual flop notation instead of initialbegin and alwaysff
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module tlb_ram #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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input [ENTRY_BITS-1:0] VPNIndex, // Index to read from
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input [ENTRY_BITS-1:0] WriteIndex,
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input [`XLEN-1:0] PageTableEntryWrite,
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input TLBWrite,
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output [`PPN_BITS-1:0] PhysicalPageNumber,
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output [7:0] PTEAccessBits
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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logic [`XLEN-1:0] ram [0:NENTRIES-1];
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logic [`XLEN-1:0] PageTableEntry;
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always @(posedge clk) begin
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if (TLBWrite) ram[WriteIndex] <= PageTableEntryWrite;
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end
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assign PageTableEntry = ram[VPNIndex];
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assign PTEAccessBits = PageTableEntry[7:0];
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assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10];
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initial begin
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for (int i = 0; i < NENTRIES; i++)
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ram[i] = `XLEN'b0;
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end
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endmodule
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35
wally-pipelined/src/mmu/tlb_rand.sv
Normal file
35
wally-pipelined/src/mmu/tlb_rand.sv
Normal file
@ -0,0 +1,35 @@
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///////////////////////////////////////////
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// tlb_rand.sv
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//
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// Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Outputs a random index for writing to the TLB.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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||||
// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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||||
//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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module tlb_rand #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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output [ENTRY_BITS-1:0] WriteIndex
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);
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logic [31:0] data;
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assign data = $urandom;
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assign WriteIndex = data[ENTRY_BITS-1:0];
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endmodule
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