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Fix bug with PC incrementing

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This commit is contained in:
Jarred Allen 2021-03-20 18:06:03 -04:00
parent a3a646d1a9
commit f9cf05a7d4
1 changed files with 1 additions and 1 deletions
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2
wally-pipelined/src/ifu/icache.sv
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@ -105,7 +105,7 @@ module icache(
assign ICacheStallF = 0; //DelayF & ~DelaySideF;
// Detect if the instruction is compressed
assign CompressedF = (DelayD) ? (MisalignedHalfInstrD[1:0] != 2'b11) : (InstrF[1:0] != 2'b11);
assign CompressedF = InstrF[1:0] != 2'b11;
// Pick the correct output, depending on whether we have to assemble this
// instruction from two reads or not.