forked from Github_Repos/cvw
updated pipeline tests
This commit is contained in:
Shriya Nadgauda
parent
a4dad3403e
commit
968994c04a
@ -69,7 +69,7 @@
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`define BOOTTIMBASE 32'h00000000
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h80000000
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`define TIMRANGE 32'h0007FFFF
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`define TIMRANGE 32'h0FFFFFFF
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`define CLINTBASE 32'h02000000
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`define CLINTRANGE 32'h0000FFFF
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`define GPIOBASE 32'h10012000
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@ -73,7 +73,7 @@
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`define BOOTTIMBASE 32'h00000000
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h80000000
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`define TIMRANGE 32'h0007FFFF
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`define TIMRANGE 32'h0FFFFFFF
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`define CLINTBASE 32'h02000000
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`define CLINTRANGE 32'h0000FFFF
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`define GPIOBASE 32'h10012000
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@ -34,9 +34,11 @@ module testbench();
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logic clk;
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logic reset;
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parameter SIGNATURESIZE = 5000000;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[0:10000];
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logic [`XLEN-1:0] signature[0:10000];
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logic [31:0] sig32[0:SIGNATURESIZE];
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logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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@ -115,6 +117,7 @@ module testbench();
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};
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string tests64i[] = '{
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"rv64i/WALLY-PIPELINE-100K", "f7ff0",
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"rv64i/I-ADD-01", "3000",
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"rv64i/I-ADDI-01", "3000",
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"rv64i/I-ADDIW-01", "3000",
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@ -260,6 +263,7 @@ module testbench();
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};
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string tests32i[] = {
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"rv32i/WALLY-PIPELINE-100K", "10a800",
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"rv32i/I-ADD-01", "2000",
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"rv32i/I-ADDI-01","2000",
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"rv32i/I-AND-01","2000",
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@ -275,7 +279,7 @@ module testbench();
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"rv32i/I-EBREAK-01","2000",
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"rv32i/I-ECALL-01","2000",
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"rv32i/I-ENDIANESS-01","2010",
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"rv32i/I-IO-01","2030",
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"rv32i/I-IO-01","2030rv",
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"rv32i/I-JAL-01","3000",
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"rv32i/I-JALR-01","3000",
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"rv32i/I-LB-01","3020",
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@ -334,8 +338,7 @@ module testbench();
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"rv32i/WALLY-CSRRC", "4000",
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"rv32i/WALLY-CSRRWI", "3000",
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"rv32i/WALLY-CSRRSI", "3000",
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"rv32i/WALLY-CSRRCI", "3000",
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"rv32i/WALLY-PIPELINE", "1a800"
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"rv32i/WALLY-CSRRCI", "3000"
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};
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string testsBP64[] = '{
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@ -358,16 +361,16 @@ module testbench();
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};
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string tests32p[] = '{
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"rv32p/WALLY-MCAUSE", "2000",
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"rv32p/WALLY-SCAUSE", "2000",
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"rv32p/WALLY-MEPC", "5000",
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"rv32p/WALLY-SEPC", "4000",
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"rv32p/WALLY-MTVAL", "5000",
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"rv32p/WALLY-STVAL", "4000",
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"rv32p/WALLY-MARCHID", "4000",
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"rv32p/WALLY-MIMPID", "4000",
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"rv32p/WALLY-MHARTID", "4000",
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"rv32p/WALLY-MVENDORID", "4000"
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// "rv32p/WALLY-MCAUSE", "2000",
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// "rv32p/WALLY-SCAUSE", "2000",
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// "rv32p/WALLY-MEPC", "5000",
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// "rv32p/WALLY-SEPC", "4000",
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// "rv32p/WALLY-MTVAL", "5000",
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// "rv32p/WALLY-STVAL", "4000",
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// "rv32p/WALLY-MARCHID", "4000",
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// "rv32p/WALLY-MIMPID", "4000",
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// "rv32p/WALLY-MHARTID", "4000",
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// "rv32p/WALLY-MVENDORID", "4000"
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};
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string tests64periph[] = '{
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@ -499,7 +502,7 @@ module testbench();
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$display("Code ended with ecall with gp = 1");
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#60; // give time for instructions in pipeline to finish
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// clear signature to prevent contamination from previous tests
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for(i=0; i<10000; i=i+1) begin
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for(i=0; i<SIGNATURESIZE; i=i+1) begin
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sig32[i] = 'bx;
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end
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@ -507,7 +510,7 @@ module testbench();
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signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
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$readmemh(signame, sig32);
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i = 0;
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while (i < 10000) begin
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while (i < SIGNATURESIZE) begin
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if (`XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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@ -513,7 +513,7 @@ class RegFile():
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for immutableRegKey, immutableRegVal in immutableRegsDict.items():
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self.regs[immutableRegKey].setValue(newValue = immutableRegVal, signed = 1)
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self.immutableRegsList.append(immutableRegKey)
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def getRandReg(self):
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reg = randint(1, len(self.regs)-1)
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while(reg in self.immutableRegsList):
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@ -584,10 +584,7 @@ class Memory():
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if addr not in self.memDict.keys():
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errStr = 'Tried to read from uninitialized address: {}'.format(addr)
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raise ReadFromUninitializedMemoryException(errStr)
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# # get a random number of grandularity
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# self.memDict[addr] = self.genRandMemoryValue()
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# get value from memory
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# print(self.memDict.items())
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val = self.memDict[addr]
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if granularity == GRANULARITY.WORD:
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val = val
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@ -638,6 +635,10 @@ class TestGen():
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self.imperasPath = imperasPath + instrSet.lower() + '/'
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self.exportTestName = 'PIPELINE'
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if (self.numInstr == 100000):
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self.exportTestName += "-100K"
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elif (self.numInstr == 1000000):
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self.exportTestName += "-1M"
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self.basename = 'WALLY-'+ self.exportTestName
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self.fname = self.imperasPath + "src/" + self.basename + ".S"
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self.refname = self.imperasPath + "references/" + self.basename + ".reference_output"
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@ -647,9 +648,9 @@ class TestGen():
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reg6 = self.model.regFile.regs[6]
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out = [Instr.issue(model = self.model, instrName = "sw", rs2 = reg, imm = imm, rs1 = reg6)]
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self.model.resultImmediateCounter += 4
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if (self.model.resultImmediateCounter == 2044):
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if (self.model.resultImmediateCounter == 2040):
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# Reset
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imm2 = Immediate.setImm12(xlen = self.xlen, value = 2044)
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imm2 = Immediate.setImm12(xlen = self.xlen, value = 2040)
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reg6.setImmutable(False)
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wreset = Instr.issue(model = self.model, instrName = "addi", rd = reg6, imm = imm2, rs1 = reg6)
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reg6.setImmutable(True)
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@ -928,14 +929,20 @@ class TestGen():
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instructions = []
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rd = self.model.regFile.getRandReg()
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memVal = self.model.memoryImmediateCounter
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reg1 = self.model.regFile.regs[7]
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memVal = self.model.memoryImmediateCounter
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self.model.memoryImmediateCounter += 4
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if (self.model.memoryImmediateCounter == 2044):
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if instr == "ld":
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if ((memVal + reg1.getValueUnsigned()) % 8) != 0:
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memVal -= 4
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self.model.memoryImmediateCounter -= 4 # we haven't read from a new location
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if (self.model.memoryImmediateCounter == 2040):
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self.model.memoryImmediateCounter = 0
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immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2044)
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immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040)
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instructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = reg1, rs1 = reg1, imm = immMem))
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@ -1062,19 +1069,19 @@ class TestGen():
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rs1 = self.model.regFile.getRandReg()
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while (rs1 == reg_pc):
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rs1 = self.model.regFile.getRandReg()
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rs1 = self.model.regFile.getRandReg()
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# TODO fix the value of rs1 - should be pc location of "1f"
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rs1.setValue(newValue = 0)
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imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
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jumpDestVal = self.model.pc.value + numInstr * 4 + 8
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generatedInstructions.append('li {}, MASK_XLEN({})'.format(rs1.regName ,jumpDestVal))
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self.model.pc += 8
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instructions.append('la {}, {}'.format(rs1.regName , "1f"))
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self.model.pc += 8
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newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm, dir = "f")
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newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm)
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instructions.append(newInstr)
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# add random alu instructions after jumping before jump point
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reg_check = self.model.regFile.getRandReg()
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for i in range(0, numInstr):
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@ -1086,6 +1093,9 @@ class TestGen():
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r2 = self.model.regFile.getRandReg()
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instructions.append(Instr.issue(model = self.model, instrName = "and", rd = rd, rs1 = r1, rs2 = r2))
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instructions.append("1:")
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self.model.pc += 4
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#make sure jump was taken
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check_instr = self.genTestInstr(reg_check)
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for check in check_instr:
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@ -1106,6 +1116,8 @@ class TestGen():
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instructions.append(newInstr)
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# instructions.append("jal x" + reg1 + ", 1f")
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instructions.append("2:")
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self.model.pc += 4
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newInstr = Instr.issue(model = self.model, instrName='jal', rd = reg2, label = label3, dir = "f")
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instructions.append(newInstr)
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@ -1121,40 +1133,47 @@ class TestGen():
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imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
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generatedInstructions.append('li {}, MASK_XLEN({})'.format(rs1.regName ,jumpDestVal))
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instructions.append('la {}, {}'.format(rs1.regName ,"2b"))
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self.model.pc += 8
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rs1 = self.model.regFile.regs[0]
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imm = Immediate.setImm12(xlen = self.model.xlen, value = jumpDestVal)
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rs1.setValue(newValue = 0) #TODO: this value is wrong, should be address of label
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imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
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numInstr = np.random.randint(0,6)
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for i in range(0, numInstr):
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rd = self.model.regFile.getRandReg()
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while(rd == rs1) or (rd == reg_pc):
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rd = self.model.regFile.getRandReg()
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r1 = self.model.regFile.getRandReg()
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r2 = self.model.regFile.getRandReg()
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instructions.append(Instr.issue(model = self.model, instrName = 'and', rd = rd, rs1 = r1, rs2 = r2))
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#test case here
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newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg2, rs1 = rs1, imm = imm, dir = "b")
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newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm)
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instructions.append(newInstr)
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# instructions.append("jal x" + reg2 + ", 2b")
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instructions.append("3:")
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self.model.pc += 4
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check_instr = self.genTestInstr(reg1)
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for check in check_instr:
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instructions.append(check)
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check_instr = self.genTestInstr(reg_pc)
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for check in check_instr:
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instructions.append(check)
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# jump to 1
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# #2
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# jump to 3
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# #1
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# junk instructions
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# ...
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# ...
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# test instruction
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# test instruction to 2
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# #3
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# check answer from 1
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return instructions
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@ -1226,17 +1245,23 @@ class TestGen():
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elif randInstr in InstrTypes['I']:
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if randInstr == "jalr":
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# newInstr = self.jumpRInstruction(instr = randInstr)
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# for i in newInstr:
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# generatedInstructions.append(i)
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continue
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newInstr = self.jumpRInstruction(instr = randInstr)
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for i in newInstr:
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generatedInstructions.append(i)
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# memory instruction
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elif randInstr[0] == 'l':
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rd = self.model.regFile.getRandReg()
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rs1 = self.model.regFile.regs[7]
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memLocation = list(self.model.memory.memDict.keys())[randint(0, len(self.model.memory.memDict.keys()) -1)]
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memLocation = list(self.model.memory.memDict.keys())[randint(0, len(self.model.memory.memDict.keys()) -1)]
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if randInstr == "ld":
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if ((memLocation + rs1.getValueUnsigned()) % 8) != 0:
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if (memLocation != 0):
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memLocation -=4
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else:
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memLocation = 4
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rd = self.model.regFile.getRandReg()
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imm12 = Immediate.setImm12(xlen = self.model.xlen, value = memLocation)
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instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, imm = imm12)
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generatedInstructions.append(instr)
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@ -1257,13 +1282,20 @@ class TestGen():
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generatedInstructions.append(testInstr)
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elif randInstr in InstrTypes['S']:
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rs2 = self.model.regFile.getRandReg()
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rs1 = self.model.regFile.regs[7]
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immValue = self.model.memoryImmediateCounter
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self.model.memoryImmediateCounter += 4
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immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2044)
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if (self.model.memoryImmediateCounter == 2044):
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if randInstr == 'Sd':
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if ((immValue + rs1.getValueUnsigned()) % 8) != 0:
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immValue -= 4
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self.model.memoryImmediateCounter -= 4 #haven't put a value in a new mem locatoin
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rs2 = self.model.regFile.getRandReg()
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immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040)
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if (self.model.memoryImmediateCounter == 2040):
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self.model.memoryImmediateCounter = 0
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generatedInstructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = rs1, rs1 = rs1, imm = immMem))
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@ -1331,7 +1363,10 @@ class TestGen():
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hexVal = int(self.model.memory.memDict[memLoc],2)
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hexDigitSize = self.model.xlen / 4
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formattedStr = '0x{0:0{1}x}'.format(hexVal, hexDigitSize)
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asmFile.write('\t.word {}\n'.format(formattedStr))
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if self.model.xlen == 64:
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asmFile.write('\t.dword {}\n'.format(formattedStr))
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else:
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asmFile.write('\t.word {}\n'.format(formattedStr))
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lineNum += 1
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asmFile.write("\n")
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@ -1685,6 +1720,148 @@ class Instr():
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return 'jal {}, {}{}'.format(rd.getRegName(), label.name, dir)
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###################################################################################################
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# RV 64I
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###################################################################################################
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#TODO These may not keep the internal model consistent. You have been warned...sorry lol
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@classmethod
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def Instr_ld(self, model, rd = None, rs1 = None, imm = None):
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addr = imm.getDecValue()
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rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD), \
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resultNumBits = model.xlen))
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model.pc += 4
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return 'ld {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
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@classmethod
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def Instr_lwu(self, model, rd = None, rs1 = None, imm = None):
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addr = imm.getDecValue()
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rd.setBits(newBits = zeroExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.BYTE), \
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resultNumBits = model.xlen))
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model.pc += 4
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return 'lwu {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
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@classmethod
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def Instr_addiw(self, model, rd = None, rs1 = None, imm = None):
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newValue = rs1.getDecValue() + imm.getDecValue()
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newValueBin = 0
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if newValue > 0:
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newValueBin = bin(newValue)[2:]
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elif newValue == 0:
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newValueBin = "0" * model.xlen
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else:
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newValueBin = bin(newValue)[3:]
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newValueBinTrunk = newValueBin[-model.xlen:]
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rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
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model.pc += 4
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return 'addiw {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
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@classmethod
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def Instr_slliw(self, model, rd = None, rs1 = None, imm = None):
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bits = rs1.bits
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immBits = imm.bits[-5:]
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immShift = int(immBits, 2)
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shifted = bits[-(len(bits) - immShift):]
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shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
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rd.setValue(newValue = shiftedExt, signed = 1)
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model.pc += 4
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return 'slliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
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@classmethod
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def Instr_srliw(self, model, rd = None, rs1 = None, imm = None):
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bits = rs1.bits
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immBits = imm.bits[-5:]
|
||||
immShift = int(immBits, 2)
|
||||
shifted = bits[0:len(bits) - immShift]
|
||||
extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
|
||||
rd.setBits(newBits = extShifted, signed = 1)
|
||||
model.pc += 4
|
||||
return 'srliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
|
||||
|
||||
@classmethod
|
||||
def Instr_sraiw(self, model, rd = None, rs1 = None, imm = None):
|
||||
bits = rs1.bits
|
||||
immBits = imm.bits[-5:]
|
||||
immShift = int(immBits, 2)
|
||||
shifted = bits[0:len(bits) - immShift]
|
||||
extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
|
||||
rd.setBits(newBits = extShifted, signed = 1)
|
||||
model.pc += 4
|
||||
return 'sraiw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
|
||||
|
||||
@classmethod
|
||||
def Instr_Sd(self, model, rs1 = None, rs2 = None, imm = None):
|
||||
addr = imm.getDecValue()
|
||||
model.memory.updateMemory(addr = addr, value = rs2.bits, granularity = GRANULARITY.WORD)
|
||||
model.pc += 4
|
||||
return 'Sd {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_addw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
newValue = rs1.getDecValue() + rs2.getDecValue()
|
||||
newValueBin = 0
|
||||
if newValue > 0:
|
||||
newValueBin = bin(newValue)[2:]
|
||||
elif newValue == 0:
|
||||
newValueBin = "0" * model.xlen
|
||||
else:
|
||||
newValueBin = bin(newValue)[3:]
|
||||
newValueBinTrunk = newValueBin[-model.xlen:]
|
||||
rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
|
||||
model.pc += 4
|
||||
return 'addw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_subw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
newValue = rs1.getDecValue() - rs2.getDecValue()
|
||||
newValueBin = 0
|
||||
if newValue > 0:
|
||||
newValueBin = bin(newValue)[2:]
|
||||
elif newValue == 0:
|
||||
newValueBin = "0" * model.xlen
|
||||
else:
|
||||
newValueBin = bin(newValue)[3:]
|
||||
newValueBinTrunk = newValueBin[-model.xlen:]
|
||||
rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
|
||||
model.pc += 4
|
||||
return 'subw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_sllw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
bits = rs1.bits
|
||||
rs2Bin = rs2.bits[-5:]
|
||||
rs2Shift = int(rs2Bin,2)
|
||||
shifted = bits[-(len(bits) - rs2Shift):]
|
||||
shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
|
||||
rd.setValue(newValue = shiftedExt, signed = 1)
|
||||
model.pc += 4
|
||||
return 'sllw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_srlw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
bits = rs1.bits
|
||||
rs2Bin = rs2.bits[-5:]
|
||||
rs2Shift = int(rs2Bin,2)
|
||||
shifted = bits[0:len(bits) - rs2Shift]
|
||||
extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
|
||||
rd.setBits(newBits = extShifted, signed = 1)
|
||||
model.pc += 4
|
||||
return 'srlw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_sraw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
bits = rs1.bits
|
||||
rs2Bin = rs2.bits[-5:]
|
||||
rs2Shift = int(rs2Bin,2)
|
||||
shifted = bits[0:len(bits) - rs2Shift]
|
||||
extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
|
||||
rd.setBits(newBits = extShifted, signed = 1)
|
||||
model.pc += 4
|
||||
return 'sraw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
|
||||
###################################################################################################
|
||||
# Global Constants
|
||||
###################################################################################################
|
||||
@ -1693,7 +1870,7 @@ GRANULARITY = Enum('granularity', ['WORD', 'HALFWORD', 'BYTE'])
|
||||
INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \
|
||||
'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \
|
||||
'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \
|
||||
'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal'], \
|
||||
'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal', 'jalr'], \
|
||||
'RV64I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \
|
||||
'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \
|
||||
'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \
|
||||
@ -1703,9 +1880,11 @@ INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti',
|
||||
}
|
||||
|
||||
|
||||
InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and'], \
|
||||
'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr'], \
|
||||
'S' : ['sw', 'sh', 'sb'], \
|
||||
InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', \
|
||||
'addw', 'subw', 'sllw', 'srlw', 'sraw'], \
|
||||
'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr', \
|
||||
'ld', 'lwu', 'addiw', 'slliw', 'srliw', 'sraiw'], \
|
||||
'S' : ['sw', 'sh', 'sb', 'Sd'], \
|
||||
'B' : ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu'], \
|
||||
'U' : ['lui', 'auipc'], \
|
||||
'J' : ['jal'], \
|
||||
@ -1714,27 +1893,25 @@ InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra',
|
||||
# Main Body
|
||||
###################################################################################################
|
||||
|
||||
XLEN = ['32']
|
||||
XLEN = ['32', '64']
|
||||
INSTRUCTION_TYPE = ['I']
|
||||
NUMINSTR = 70000
|
||||
NUMINSTR = [100000, 1000000]
|
||||
IMPERASPATH = "../../imperas-riscv-tests/riscv-test-suite/"
|
||||
|
||||
seed(42)
|
||||
np.random.seed(42)
|
||||
for xlen in XLEN:
|
||||
memInit = {}
|
||||
for i in range(0, 400, 4):
|
||||
val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1)
|
||||
memInit[i] = val
|
||||
for instrType in INSTRUCTION_TYPE:
|
||||
instrSet = 'RV' + xlen + instrType
|
||||
|
||||
print('Generating Assembly for {}'.format(instrSet))
|
||||
|
||||
dut = TestGen(numInstr=NUMINSTR, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH)
|
||||
# regFile =
|
||||
dut.model.memory.populateMemory(memDict = memInit)
|
||||
dut.exportASM(instrSet = instrSet, instrTypes = instrType)
|
||||
|
||||
|
||||
for num_instructions in NUMINSTR:
|
||||
for xlen in XLEN:
|
||||
memInit = {}
|
||||
for i in range(0, 400, 4):
|
||||
val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1)
|
||||
memInit[i] = val
|
||||
for instrType in INSTRUCTION_TYPE:
|
||||
instrSet = 'RV' + xlen + instrType
|
||||
|
||||
print('Generating {} Assembly Instructions for {}'.format(num_instructions, instrSet))
|
||||
|
||||
dut = TestGen(numInstr=num_instructions, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH)
|
||||
# regFile =
|
||||
dut.model.memory.populateMemory(memDict = memInit)
|
||||
dut.exportASM(instrSet = instrSet, instrTypes = instrType)
|
||||
Loading…
Reference in New Issue
Block a user