forked from Github_Repos/cvw
More memory interface, ALU testgen
This commit is contained in:
David Harris
parent
183a2dcfb5
commit
37dba8fd26
@ -38,9 +38,8 @@ module ahblite (
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// Signals from Instruction Cache
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input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram
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input logic InstrReadF,
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input logic ResolveBranchD,
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// input logic ResolveBranchD,
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output logic [31:0] InstrRData,
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// output logic IReady,
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// Signals from Data Cache
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input logic [`XLEN-1:0] MemPAdrM,
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input logic MemReadM, MemWriteM,
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@ -48,7 +47,6 @@ module ahblite (
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input logic [1:0] MemSizeM,
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// Return from bus
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output logic [`XLEN-1:0] ReadDataW,
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// output logic DReady,
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// AHB-Lite external signals
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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@ -61,14 +59,12 @@ module ahblite (
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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// Delayed signals for subword write
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// Delayed signals for writes
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output logic [2:0] HADDRD,
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output logic [3:0] HSIZED,
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output logic HWRITED,
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// Acknowledge
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output logic InstrAckD, MemAckW,
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// Stalls
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output logic InstrStall, DataStall
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output logic InstrStall,/*InstrUpdate, */DataStall
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);
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logic GrantData;
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@ -81,12 +77,61 @@ module ahblite (
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assign HCLK = clk;
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assign HRESETn = ~reset;
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// Arbitrate requests by giving data priority over instructions
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assign GrantData = MemReadM | MemWriteM;
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// *** initially support HABW = XLEN
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// track bus state
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// Data accesses have priority over instructions. However, if a data access comes
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// while an instruction read is occuring, the instruction read finishes before
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// the data access can take place.
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typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADMEMPENDING} statetype;
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statetype BusState, NextBusState;
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) BusState <= #1 IDLE;
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else BusState <= #1 NextBusState;
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always_comb
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case (BusState)
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IDLE: if (MemReadM) NextBusState = MEMREAD; // Memory has pirority over instructions
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else if (MemWriteM) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMREAD: if (~HREADY) NextBusState = MEMREAD;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMWRITE: if (~HREADY) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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INSTRREAD: //if (~HREADY & (MemReadM | MemWriteM)) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete
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if (~HREADY) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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INSTRREADMEMPENDING: if (~HREADY) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete
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else if (MemReadM) NextBusState = MEMREAD;
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else NextBusState = MEMWRITE; // must be write if not a read. Don't return to idle.
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endcase
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// stall signals
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assign #2 DataStall = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || (NextBusState == INSTRREADMEMPENDING);
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assign #1 InstrStall = (NextBusState == INSTRREAD);
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// assign InstrUpdate = (BusState == INSTRREADMEMPENDING) && (NextBusState != INSTRREADMEMPENDING);
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// bus outputs
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assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
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assign #1 HADDR = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0];
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assign #1 HSIZE = GrantData ? {1'b0, MemSizeM} : ISize;
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assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
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assign HMASTLOCK = 0; // no locking supported
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assign HWRITE = (NextBusState == MEMWRITE);
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// delay write data by one cycle for
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flop #(`XLEN) wdreg(HCLK, WriteDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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// delay signals for subword writes
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flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
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flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
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flop #(1) writereg(HCLK, HWRITE, HWRITED);
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/*
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typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
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statetype AdrState, DataState, NextAdrState; // what is happening in the first and second phases of the bus
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always_ff @(posedge HCLK, negedge HRESETn)
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@ -117,13 +162,42 @@ module ahblite (
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assign MemAckW = (AdrState == MEMREAD || AdrState == MEMWRITE) && HREADY;
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assign InstrAckD = (AdrState == INSTRREAD) && HREADY;
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// State machines for stalls (probably can merge with FSM above***)
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// Idle, DataBusy, InstrBusy. Stall while in busystate add suffixes
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logic MemState, NextMemState, InstrState, NextInstrState;
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flopr #(1) msreg(HCLK, ~HRESETn, NextMemState, MemState);
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flopr #(1) isreg(HCLK, ~HRESETn, NextInstrState, InstrState);
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/* always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) MemState <= 0;
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else MemState <= NextMemState;
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assign NextMemState = (MemState == 0 && InstrState == 0 && (MemReadM || MemWriteM)) || (MemState == 1 && ~MemAckW);
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assign DataStall = NextMemState;
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/* always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) InstrState <= 0;
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else InstrState <= NextInstrState;
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assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) ||
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(InstrState == 1 && ~InstrAckD) ||
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(InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later
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/* assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM)) ||
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(InstrState == 1 && ~InstrAckD); // *** removed InstrReadF above dh 2/9/20
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assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better
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// temporarily turn off stalls and check it works
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//assign DataStall = 0;
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//assign InstrStall = 0;
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assign DReady = HREADY & GrantData; // ***unused?
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assign IReady = HREADY & InstrReadF & ~GrantData; // maybe unused?***
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*/
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// Choose ISize based on XLen
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generate
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//if (`AHBW == 32) assign ISize = 3'b010; // 32-bit transfers
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//else assign ISize = 3'b011; // 64-bit transfers
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assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width
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endgenerate
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/*
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// drive bus outputs
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assign HADDR = GrantData ? MemPAdrM[31:0] : InstrPAdrF[31:0];
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//assign HWDATA = WriteDataW;
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@ -134,41 +208,16 @@ module ahblite (
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HTRANS = InstrReadF | MemReadM | MemWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
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assign HMASTLOCK = 0; // no locking supported
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*/
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// Route signals to Instruction and Data Caches
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// *** assumes AHBW = XLEN
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assign InstrRData = HRDATAMasked[31:0];
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assign IReady = HREADY & InstrReadF & ~GrantData; // maybe unused?***
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// assign ReadDataW = HRDATAMasked;
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assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
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flopenrc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ~StallW, ReadDataM, ReadDataW);
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assign DReady = HREADY & GrantData; // ***unused?
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assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD);
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flopenr #(`XLEN) ReadDataWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataW);
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// State machines for stalls (probably can merge with FSM above***)
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// Idle, DataBusy, InstrBusy. Stall while in busystate add suffixes
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logic MemState, NextMemState, InstrState, NextInstrState;
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flopr #(1) msreg(HCLK, ~HRESETn, NextMemState, MemState);
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flopr #(1) isreg(HCLK, ~HRESETn, NextInstrState, InstrState);
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/* always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) MemState <= 0;
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else MemState <= NextMemState; */
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assign NextMemState = (MemState == 0 && InstrState == 0 && (MemReadM || MemWriteM)) || (MemState == 1 && ~MemAckW);
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assign DataStall = NextMemState;
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/* always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) InstrState <= 0;
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else InstrState <= NextInstrState;*/
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assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) ||
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(InstrState == 1 && ~InstrAckD) ||
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(InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later
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/* assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM)) ||
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(InstrState == 1 && ~InstrAckD); // *** removed InstrReadF above dh 2/9/20 */
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assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better
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// temporarily turn off stalls and check it works
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//assign DataStall = 0;
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//assign InstrStall = 0;
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// stalls
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// Stall MEM stage if data is being accessed and bus isn't yet ready
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//assign DataStall = GrantData & ~HREADY;
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@ -47,6 +47,16 @@ module flopr #(parameter WIDTH = 8) (
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else q <= #1 d;
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endmodule
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// flop with enable
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module flopen #(parameter WIDTH = 8) (
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input logic clk, en,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk)
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if (en) q <= #1 d;
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endmodule
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// flop with enable, asynchronous reset, synchronous clear
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module flopenrc #(parameter WIDTH = 8) (
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input logic clk, reset, clear, en,
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@ -56,12 +56,12 @@ module hazard(
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assign BranchFlushDE = PCSrcE | RetM | TrapM;
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assign StallFCause = InstrStall | CSRWritePendingDEM; // stall at fetch if unable to get the instruction,
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assign StallFCause = /*InstrStall | */ CSRWritePendingDEM; // stall at fetch if unable to get the instruction,
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// or if a CSR will be written and may change system behavior
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assign StallDCause = LoadStallD; // stall in decode if instruction is a load dependent on previous
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assign StallECause = 0;
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assign StallMCause = 0; // sDataStall; // not yet used***
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assign StallWCause = DataStall; // | InstrStall;
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assign StallWCause = DataStall | InstrStall;
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// Each stage stalls if the next stage is stalled or there is a cause to stall this stage.
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assign StallF = StallD | StallFCause;
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@ -67,18 +67,20 @@ module ifu (
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// *** put memory interface on here, InstrF becomes output
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assign InstrPAdrF = PCF; // *** no MMU
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assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
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//assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
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assign InstrReadF = 1; // *** & ICacheMissF; add later
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assign PrivilegedChangePCM = RetM | TrapM;
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assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM);
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//assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM);
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// dh 2/8/2022 keep in instruction fetch stall mode when taking branch
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flopr #(1) rbreg(clk, reset, (PCSrcE | PrivilegedChangePCM), ResolveBranchD);
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//flopr #(1) rbreg(clk, reset, (PCSrcE | PrivilegedChangePCM), ResolveBranchD);
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mux3 #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF);
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assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
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flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF);
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// flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF);
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flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
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// pcadder
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// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
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@ -28,7 +28,7 @@
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module csr (
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input logic clk, reset,
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input logic FlushW,
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input logic FlushW, StallW,
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input logic [31:0] InstrM,
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input logic [`XLEN-1:0] PCM, SrcAM,
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input logic CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
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@ -27,7 +27,7 @@
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`include "wally-config.vh"
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module csrsr (
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input logic clk, reset,
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input logic clk, reset, StallW,
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input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM,
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input logic TrapM, FloatRegWriteW,
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input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
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@ -118,7 +118,7 @@ module csrsr (
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STATUS_MIE <= 0; // Per Priv 3.3
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STATUS_SIE <= `S_SUPPORTED;
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STATUS_UIE <= `U_SUPPORTED;
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end else begin
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end else if (~StallW) begin
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if (WriteMSTATUSM) begin
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STATUS_SUM_INT <= CSRWriteValM[18];
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STATUS_MPRV_INT <= CSRWriteValM[17];
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// exceptions.sv
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// privileged.sv
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//
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// Written: David_Harris@hmc.edu 5 January 2021
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// Modified:
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@ -45,7 +45,7 @@ module privileged (
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input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
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input logic [4:0] SetFflagsM,
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output logic [2:0] FRM_REGW,
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input logic FlushD, FlushE, FlushM, StallD
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input logic FlushD, FlushE, FlushM, StallD, StallW
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);
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logic [1:0] NextPrivilegeModeM, PrivilegeModeW;
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@ -81,8 +81,8 @@ module privileged (
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// PrivilegeMode FSM
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always_comb
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if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode)
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else if (mretM) NextPrivilegeModeM = STATUS_MPP;
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/* if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode) // moved reset to flop
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else */ if (mretM) NextPrivilegeModeM = STATUS_MPP;
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else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP};
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else if (uretM) NextPrivilegeModeM = `U_MODE;
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else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
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@ -96,7 +96,7 @@ module privileged (
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else NextPrivilegeModeM = `M_MODE;
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end else NextPrivilegeModeM = PrivilegeModeW;
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flop #(2) privmodereg(clk, NextPrivilegeModeM, PrivilegeModeW);
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flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
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///////////////////////////////////////////
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// decode privileged instructions
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@ -37,6 +37,7 @@ module dtim (
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logic [`XLEN-1:0] RAM[0:65535];
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logic [18:0] HWADDR;
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logic [`XLEN-1:0] HREADTim0;
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// logic [`XLEN-1:0] write;
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logic [15:0] entry;
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@ -44,27 +45,28 @@ module dtim (
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logic [3:0] busycount;
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// busy FSM to extend READY signal
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/* always_ff @(posedge HCLK, negedge HRESETn)
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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HREADYTim <= 1;
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end else begin
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if (HREADYTim & HSELTim) begin
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busycount <= 0;
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HREADYTim <= 0;
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HREADYTim <= #1 0;
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end else if (~HREADYTim) begin
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if (busycount == 0) begin // TIM latency, for testing purposes
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HREADYTim <= 1;
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if (busycount == 2) begin // TIM latency, for testing purposes
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HREADYTim <= #1 1;
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end else begin
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busycount <= busycount + 1;
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end
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end
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end*/
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always_ff @(posedge HCLK, negedge HRESETn)
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end
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/* always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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HREADYTim <= 0;
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end else begin
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HREADYTim <= HSELTim; // always respond one cycle later
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end
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end */
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assign memread = MemRWtim[1];
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@ -73,77 +75,32 @@ module dtim (
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// memwrite <= MemRWtim[0]; // delay memwrite to write phase
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assign HRESPTim = 0; // OK
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// assign HREADYTim = 1; // Respond immediately; *** extend this
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// word aligned reads
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/* generate
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if (`XLEN==64)
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assign #2 entry = HADDR[18:3];
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else
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assign #2 entry = HADDR[17:2];
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endgenerate */
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// assign HREADTim = RAM[entry];
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// assign HREADTim = HREADYTim ? RAM[entry] : ~RAM[entry]; // *** temproary mess up read value before ready
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// write each byte based on the byte mask
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// UInstantiate a byte-writable memory here if possible
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// and drop tihs masking logic. Otherwise, use the masking
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// from dmem
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/*generate
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if (`XLEN==64) begin
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always_comb begin
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write=HREADTim;
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if (ByteMaskM[0]) write[7:0] = HWDATA[7:0];
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if (ByteMaskM[1]) write[15:8] = HWDATA[15:8];
|
||||
if (ByteMaskM[2]) write[23:16] = HWDATA[23:16];
|
||||
if (ByteMaskM[3]) write[31:24] = HWDATA[31:24];
|
||||
if (ByteMaskM[4]) write[39:32] = HWDATA[39:32];
|
||||
if (ByteMaskM[5]) write[47:40] = HWDATA[47:40];
|
||||
if (ByteMaskM[6]) write[55:48] = HWDATA[55:48];
|
||||
if (ByteMaskM[7]) write[63:56] = HWDATA[63:56];
|
||||
end
|
||||
always_ff @(posedge clk)
|
||||
if (memwrite) RAM[HADDR[18:3]] <= write;
|
||||
end else begin // 32-bit
|
||||
always_comb begin
|
||||
write=HREADTim;
|
||||
if (ByteMaskM[0]) write[7:0] = HWDATA[7:0];
|
||||
if (ByteMaskM[1]) write[15:8] = HWDATA[15:8];
|
||||
if (ByteMaskM[2]) write[23:16] = HWDATA[23:16];
|
||||
if (ByteMaskM[3]) write[31:24] = HWDATA[31:24];
|
||||
end
|
||||
always_ff @(posedge clk)
|
||||
if (memwrite) RAM[HADDR[17:2]] <= write;
|
||||
end
|
||||
endgenerate */
|
||||
|
||||
// Model memory read and write
|
||||
// If write occurs at end of phase (rising edge of clock),
|
||||
// then read of same address on next cycle won't work. Would need to bypass.
|
||||
// Faking for now with negedge clock write. Will need to adjust this to
|
||||
// match capabilities of FPGA or actual chip RAM.
|
||||
// Also, writes occuring later than reads throws off single ported RAM that
|
||||
// might be asked to write on one instruction and read on the next and would need
|
||||
// to stall because both accesses happen on same cycle with AHB delay
|
||||
|
||||
generate
|
||||
if (`XLEN == 64) begin
|
||||
always_ff @(negedge HCLK)
|
||||
if (memwrite) RAM[HWADDR[17:3]] <= HWDATA;
|
||||
// always_ff @(negedge HCLK)
|
||||
// if (memwrite) RAM[HWADDR[17:3]] <= HWDATA;
|
||||
always_ff @(posedge HCLK) begin
|
||||
//if (memwrite) RAM[HADDR[17:3]] <= HWDATA;
|
||||
HWADDR <= HADDR;
|
||||
HREADTim <= RAM[HADDR[17:3]];
|
||||
HREADTim0 <= RAM[HADDR[17:3]];
|
||||
if (memwrite && HREADYTim) RAM[HWADDR[17:3]] <= HWDATA;
|
||||
end
|
||||
end else begin
|
||||
always_ff @(negedge HCLK)
|
||||
if (memwrite) RAM[HWADDR[17:2]] <= HWDATA;
|
||||
// always_ff @(negedge HCLK)
|
||||
// if (memwrite) RAM[HWADDR[17:2]] <= HWDATA;
|
||||
always_ff @(posedge HCLK) begin
|
||||
//if (memwrite) RAM[HADDR[17:2]] <= HWDATA;
|
||||
HWADDR <= HADDR;
|
||||
HREADTim <= RAM[HADDR[17:2]];
|
||||
HREADTim0 <= RAM[HADDR[17:2]];
|
||||
if (memwrite && HREADYTim) RAM[HWADDR[17:2]] <= HWDATA;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign HREADTim = HREADYTim ? HREADTim0 : 'bz;
|
||||
endmodule
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#!/usr/bin/python3
|
||||
##################################
|
||||
# testgen-ADD-SUB.py
|
||||
# testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
|
||||
#
|
||||
# David_Harris@hmc.edu 19 January 2021
|
||||
#
|
||||
@ -19,11 +19,34 @@ from random import getrandbits
|
||||
# functions
|
||||
##################################
|
||||
|
||||
def computeExpected(a, b, test):
|
||||
def twoscomp(a):
|
||||
amsb = a >> (xlen-1)
|
||||
alsbs = ((1 << (xlen-1)) - 1) & a
|
||||
if (amsb):
|
||||
asigned = a - (1<<xlen)
|
||||
else:
|
||||
asigned = a
|
||||
#print("a: " + str(a) + " amsb: "+str(amsb)+ " alsbs: " + str(alsbs) + " asigned: "+str(asigned))
|
||||
return asigned
|
||||
|
||||
def computeExpected(a, b, test, xlen):
|
||||
asigned = twoscomp(a)
|
||||
bsigned = twoscomp(b)
|
||||
|
||||
if (test == "ADD"):
|
||||
return a + b
|
||||
elif (test == "SUB"):
|
||||
return a - b
|
||||
elif (test == "SLT"):
|
||||
return asigned < bsigned
|
||||
elif (test == "SLTU"):
|
||||
return a < b
|
||||
elif (test == "XOR"):
|
||||
return a ^ b
|
||||
elif (test == "OR"):
|
||||
return a | b
|
||||
elif (test == "AND"):
|
||||
return a & b
|
||||
else:
|
||||
die("bad test name ", test)
|
||||
# exit(1)
|
||||
@ -37,9 +60,9 @@ def randRegs():
|
||||
else:
|
||||
return reg1, reg2, reg3
|
||||
|
||||
def writeVector(a, b, storecmd):
|
||||
def writeVector(a, b, storecmd, xlen):
|
||||
global testnum
|
||||
expected = computeExpected(a, b, test)
|
||||
expected = computeExpected(a, b, test, xlen)
|
||||
expected = expected % 2**xlen # drop carry if necessary
|
||||
if (expected < 0): # take twos complement
|
||||
expected = 2**xlen + expected
|
||||
@ -65,7 +88,7 @@ def writeVector(a, b, storecmd):
|
||||
##################################
|
||||
|
||||
# change these to suite your tests
|
||||
tests = ["ADD", "SUB"]
|
||||
tests = ["ADD", "SUB", "SLT", "SLTU", "XOR", "OR", "AND"]
|
||||
author = "David_Harris@hmc.edu & Katherine Parry"
|
||||
xlens = [32, 64]
|
||||
numrand = 100;
|
||||
@ -111,11 +134,11 @@ for xlen in xlens:
|
||||
# print directed and random test vectors
|
||||
for a in corners:
|
||||
for b in corners:
|
||||
writeVector(a, b, storecmd)
|
||||
writeVector(a, b, storecmd, xlen)
|
||||
for i in range(0,numrand):
|
||||
a = getrandbits(xlen)
|
||||
b = getrandbits(xlen)
|
||||
writeVector(a, b, storecmd)
|
||||
writeVector(a, b, storecmd, xlen)
|
||||
|
||||
|
||||
# print footer
|
||||
154
wally-pipelined/testgen/testgen-SLL-SRL-SRA.py
Executable file
154
wally-pipelined/testgen/testgen-SLL-SRL-SRA.py
Executable file
@ -0,0 +1,154 @@
|
||||
#!/usr/bin/python3
|
||||
##################################
|
||||
# testgen-SLL-SRL-SRA.py
|
||||
#
|
||||
# David_Harris@hmc.edu 19 January 2021
|
||||
#
|
||||
# Generate directed and random test vectors for RISC-V Design Validation.
|
||||
##################################
|
||||
|
||||
##################################
|
||||
# libraries
|
||||
##################################
|
||||
from datetime import datetime
|
||||
from random import randint
|
||||
from random import seed
|
||||
from random import getrandbits
|
||||
|
||||
##################################
|
||||
# functions
|
||||
##################################
|
||||
|
||||
def twoscomp(a):
|
||||
amsb = a >> (xlen-1)
|
||||
alsbs = ((1 << (xlen-1)) - 1) & a
|
||||
if (amsb):
|
||||
asigned = a - (1<<xlen)
|
||||
else:
|
||||
asigned = a
|
||||
#print("a: " + str(a) + " amsb: "+str(amsb)+ " alsbs: " + str(alsbs) + " asigned: "+str(asigned))
|
||||
return asigned
|
||||
|
||||
def computeExpected(a, b, test, xlen):
|
||||
asigned = twoscomp(a)
|
||||
b = b % xlen
|
||||
if (test == "SLL"):
|
||||
return a << b
|
||||
elif (test == "SRL"):
|
||||
return a >> b
|
||||
elif (test == "SRA"):
|
||||
return asigned >> b
|
||||
else:
|
||||
die("bad test name ", test)
|
||||
# exit(1)
|
||||
|
||||
def randRegs():
|
||||
reg1 = randint(1,31)
|
||||
reg2 = randint(1,31)
|
||||
reg3 = randint(1,31)
|
||||
if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
|
||||
return randRegs()
|
||||
else:
|
||||
return reg1, reg2, reg3
|
||||
|
||||
def writeVector(a, b, storecmd, xlen):
|
||||
global testnum
|
||||
expected = computeExpected(a, b, test, xlen)
|
||||
expected = expected % 2**xlen # drop carry if necessary
|
||||
if (expected < 0): # take twos complement
|
||||
expected = 2**xlen + expected
|
||||
reg1, reg2, reg3 = randRegs()
|
||||
lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a)
|
||||
lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b)
|
||||
lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
|
||||
lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
|
||||
lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
|
||||
lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
|
||||
lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
|
||||
lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
|
||||
f.write(lines)
|
||||
if (xlen == 32):
|
||||
line = formatrefstr.format(expected)+"\n"
|
||||
else:
|
||||
line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
|
||||
r.write(line)
|
||||
testnum = testnum+1
|
||||
|
||||
##################################
|
||||
# main body
|
||||
##################################
|
||||
|
||||
# change these to suite your tests
|
||||
tests = ["SLL", "SRL", "SRA"]
|
||||
author = "David_Harris@hmc.edu"
|
||||
xlens = [32, 64]
|
||||
numrand = 48
|
||||
|
||||
# setup
|
||||
seed(0) # make tests reproducible
|
||||
|
||||
# generate files for each test
|
||||
for xlen in xlens:
|
||||
formatstrlen = str(int(xlen/4))
|
||||
formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
|
||||
formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
|
||||
if (xlen == 32):
|
||||
storecmd = "sw"
|
||||
wordsize = 4
|
||||
else:
|
||||
storecmd = "sd"
|
||||
wordsize = 8
|
||||
for test in tests:
|
||||
corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
|
||||
2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
|
||||
if (xlen == 32):
|
||||
shamt = [0, 1, 2, 3, 4, 8, 15, 16, 29, 30, 31]
|
||||
else:
|
||||
shamt = [0, 1, 3, 8, 15, 16, 29, 31, 32, 47, 48, 62, 63]
|
||||
|
||||
imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
|
||||
basename = "WALLY-" + test
|
||||
fname = imperaspath + "src/" + basename + ".S"
|
||||
refname = imperaspath + "references/" + basename + ".reference_output"
|
||||
testnum = 0
|
||||
|
||||
# print custom header part
|
||||
f = open(fname, "w")
|
||||
r = open(refname, "w")
|
||||
line = "///////////////////////////////////////////\n"
|
||||
f.write(line)
|
||||
lines="// "+fname+ "\n// " + author + "\n"
|
||||
f.write(lines)
|
||||
line ="// Created " + str(datetime.now())
|
||||
f.write(line)
|
||||
|
||||
# insert generic header
|
||||
h = open("testgen_header.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# print directed and random test vectors
|
||||
for a in corners:
|
||||
for b in shamt:
|
||||
writeVector(a, b, storecmd, xlen)
|
||||
for i in range(0,numrand):
|
||||
a = getrandbits(xlen)
|
||||
b = getrandbits(xlen)
|
||||
writeVector(a, b, storecmd, xlen)
|
||||
|
||||
|
||||
# print footer
|
||||
h = open("testgen_footer.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# Finish
|
||||
lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
|
||||
lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
|
||||
f.write(lines)
|
||||
f.close()
|
||||
r.close()
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user