forked from Github_Repos/cvw
Added the ability to exclude branch predictor.
This commit is contained in:
Ross Thompson
parent
afbb100860
commit
72363f5c66
wally-pipelined
config
buildroot
busybear
coremark
coremark_bare
rv32ic
rv64BP
rv64ic
rv64icfd
rv64imc
regression
src/ifu
testbench
@ -105,4 +105,6 @@
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`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
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`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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@ -107,4 +107,7 @@
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`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
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`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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`define BPRED_ENABLED 1
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@ -107,5 +107,6 @@
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`define TWO_BIT_PRELOAD "../config/coremark/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/coremark/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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@ -104,5 +104,6 @@
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`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE"
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`define TESTSBP 0
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@ -105,5 +105,6 @@
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`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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@ -97,5 +97,6 @@
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`define TWO_BIT_PRELOAD "../config/rv64icfd/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv64icfd/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 1
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@ -108,5 +108,7 @@
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`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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@ -101,5 +101,6 @@
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`define TWO_BIT_PRELOAD "../config/rv64icfd/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv64icfd/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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@ -104,5 +104,6 @@
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`define TWO_BIT_PRELOAD "../config/rv64imc/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/rv64imc/BTBPredictor.txt"
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`define BPRED_ENABLED 1
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`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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@ -3,9 +3,6 @@ quietly virtual function -install /testbench/dut/hart/ifu/icache/cachemem -env /
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/test
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add wave -noupdate -radix ascii /testbench/memfilename
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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@ -22,13 +19,13 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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@ -39,24 +36,25 @@ add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbe
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -expand -group direction -divider Update
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add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdatePC
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add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdateEN
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add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdatePrediction
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
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add wave -noupdate -group Bpred -group BTB -divider Update
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -group BTB -divider Lookup
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPPredF
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
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add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePC
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdateEN
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePrediction
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -expand -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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@ -89,33 +87,33 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -expand -group alu -divider internals
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -expand -group {dcache memory} /testbench/dut/hart/dmem/MemReadM
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add wave -noupdate -expand -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM
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add wave -noupdate -expand -group {dcache memory} /testbench/dut/hart/dmem/MemAckW
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add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/MemRWM
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add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/AtomicM
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add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
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add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/ReadDataW
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add wave -noupdate -expand -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
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add wave -noupdate -expand -group dcache -color Gray90 /testbench/dut/hart/dmem/CurrState
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add wave -noupdate -expand -group dcache /testbench/dut/hart/MemPAdrM
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add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemAccessM
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add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/AtomicMaskedM
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add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemAckW
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add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/genblk1/lrM
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add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/genblk1/scM
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemReadM
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add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM
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add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemAckW
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/MemRWM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/AtomicM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/dmem/ReadDataW
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
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add wave -noupdate -group dcache -color Gray90 /testbench/dut/hart/dmem/CurrState
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add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
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add wave -noupdate -group dcache /testbench/dut/hart/dmem/MemAccessM
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add wave -noupdate -group dcache /testbench/dut/hart/dmem/AtomicMaskedM
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add wave -noupdate -group dcache /testbench/dut/hart/dmem/MemAckW
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add wave -noupdate -group dcache /testbench/dut/hart/dmem/genblk1/lrM
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add wave -noupdate -group dcache /testbench/dut/hart/dmem/genblk1/scM
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -140,21 +138,6 @@ add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr
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add wave -noupdate -group {function radix debug} -radix unsigned /testbench/functionRadix/function_radix/ProgramAddrIndex
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/reset
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapLineCount
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapLine
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapFP
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapFile
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrMapLineCount
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrMapLine
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrMapFP
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrMapFile
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/pc
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrIndex
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionName
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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@ -174,75 +157,76 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
|
||||
add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||
add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBByteLength
|
||||
add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBOFFETWIDTH
|
||||
add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/BlockByteLength
|
||||
add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/OFFSETWIDTH
|
||||
add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE
|
||||
add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL
|
||||
add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWritePAdr
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadTag
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadAddr
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadPAdr
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WritePAdr
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteSet
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteTag
|
||||
add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
|
||||
add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
|
||||
add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
|
||||
add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD
|
||||
add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCNextPF
|
||||
add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
|
||||
add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
|
||||
add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPFinalF
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/BusState
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HCLK
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRDATA
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HREADY
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRESP
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDR
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWDATA
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITE
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZE
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HBURST
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HPROT
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HTRANS
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HMASTLOCK
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDRD
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||
add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||
add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBByteLength
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBOFFETWIDTH
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/BlockByteLength
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/OFFSETWIDTH
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWritePAdr
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadTag
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadAddr
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadPAdr
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WritePAdr
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteSet
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteTag
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
|
||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
|
||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
|
||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen
|
||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD
|
||||
add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCNextPF
|
||||
add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
|
||||
add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
|
||||
add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPFinalF
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/BusState
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWDATA
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITE
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZE
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HBURST
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HPROT
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||
add wave -noupdate /testbench/dut/hart/dmem/genblk1/scM
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {12215488 ns} 0} {{Cursor 4} {12211487 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
WaveRestoreCursors {{Cursor 2} {12215488 ns} 0} {{Cursor 4} {22127 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 513
|
||||
configure wave -justifyvalue left
|
||||
@ -257,4 +241,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {12215315 ns} {12215675 ns}
|
||||
WaveRestoreZoom {21993 ns} {22181 ns}
|
||||
|
||||
@ -152,29 +152,41 @@ module ifu (
|
||||
flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF);
|
||||
|
||||
// branch and jump predictor
|
||||
// I am making the port connection explicit for now as I want to see them and they will be changing.
|
||||
bpred bpred(.clk(clk),
|
||||
.reset(reset),
|
||||
.StallF(StallF),
|
||||
.StallD(StallD),
|
||||
.StallE(StallE),
|
||||
.FlushF(FlushF),
|
||||
.FlushD(FlushD),
|
||||
.FlushE(FlushE),
|
||||
.PCNextF(PCNextF),
|
||||
.BPPredPCF(BPPredPCF),
|
||||
.SelBPPredF(SelBPPredF),
|
||||
.PCE(PCE),
|
||||
.PCSrcE(PCSrcE),
|
||||
.PCTargetE(PCTargetE),
|
||||
.PCD(PCD),
|
||||
.PCLinkE(PCLinkE),
|
||||
.InstrClassE(InstrClassE),
|
||||
.BPPredWrongE(BPPredWrongE),
|
||||
.BPPredDirWrongE(BPPredDirWrongE),
|
||||
.BTBPredPCWrongE(BTBPredPCWrongE),
|
||||
.RASPredPCWrongE(RASPredPCWrongE),
|
||||
.BPPredClassNonCFIWrongE(BPPredClassNonCFIWrongE));
|
||||
generate
|
||||
if (`BPRED_ENABLED == 1) begin : bpred
|
||||
// I am making the port connection explicit for now as I want to see them and they will be changing.
|
||||
bpred bpred(.clk(clk),
|
||||
.reset(reset),
|
||||
.StallF(StallF),
|
||||
.StallD(StallD),
|
||||
.StallE(StallE),
|
||||
.FlushF(FlushF),
|
||||
.FlushD(FlushD),
|
||||
.FlushE(FlushE),
|
||||
.PCNextF(PCNextF),
|
||||
.BPPredPCF(BPPredPCF),
|
||||
.SelBPPredF(SelBPPredF),
|
||||
.PCE(PCE),
|
||||
.PCSrcE(PCSrcE),
|
||||
.PCTargetE(PCTargetE),
|
||||
.PCD(PCD),
|
||||
.PCLinkE(PCLinkE),
|
||||
.InstrClassE(InstrClassE),
|
||||
.BPPredWrongE(BPPredWrongE),
|
||||
.BPPredDirWrongE(BPPredDirWrongE),
|
||||
.BTBPredPCWrongE(BTBPredPCWrongE),
|
||||
.RASPredPCWrongE(RASPredPCWrongE),
|
||||
.BPPredClassNonCFIWrongE(BPPredClassNonCFIWrongE));
|
||||
end else begin : bpred
|
||||
assign BPPredPCF = {`XLEN{1'b0}};
|
||||
assign SelBPPredF = 1'b0;
|
||||
assign BPPredWrongE = PCSrcE;
|
||||
assign BPPredDirWrongE = 1'b0;
|
||||
assign BTBPredPCWrongE = 1'b0;
|
||||
assign RASPredPCWrongE = 1'b0;
|
||||
assign BPPredClassNonCFIWrong = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
// The true correct target is PCTargetE if PCSrcE is 1 else it is the fall through PCLinkE.
|
||||
assign PCCorrectE = PCSrcE ? PCTargetE : PCLinkE;
|
||||
|
||||
|
||||
@ -569,11 +569,16 @@ module testbench();
|
||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
|
||||
// initialize the branch predictor
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
|
||||
end
|
||||
generate
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1) begin : bpred
|
||||
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user