forked from Github_Repos/cvw
Generalize tlb module
- number of tlb entries is now parameterized - tlb now supports rv64i
This commit is contained in:
Thomas Fleming
parent
21552eaf9d
commit
347275e7ee
@ -2,19 +2,22 @@ module testbench();
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logic clk, reset;
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// DUT inputs
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logic [31:0] PCF;
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logic [31:0] PageTableEntryF;
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logic ITLBWriteF, ITLBFlushF;
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logic [`XLEN-1:0] SATP;
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logic [`XLEN-1:0] VirtualAddress;
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logic [`XLEN-1:0] PageTableEntryWrite;
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logic TLBWrite, TLBFlush;
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// DUT outputs
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logic [31:0] PCPF;
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logic ITLBMissF, ITLBHitF;
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logic [`XLEN-1:0] PhysicalAddress;
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logic TLBMiss, TLBHit;
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// Testbench signals
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logic [33:0] expected;
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logic [31:0] vectornum, errors;
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logic [99:0] testvectors[10000:0];
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assign SATP = {1'b1, 31'b0};
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// instantiate device under test
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tlb_toy dut(.*);
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@ -31,17 +34,17 @@ module testbench();
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// apply test vectors on rising edge of clk
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always @(posedge clk) begin
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#1; {PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF, expected} = testvectors[vectornum];
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#1; {VirtualAddress, PageTableEntryWrite, TLBWrite, TLBFlush, expected} = testvectors[vectornum];
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end
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// check results on falling edge of clk
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always @(negedge clk)
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if (~reset) begin // skip during reset
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if ({PCPF, ITLBMissF, ITLBHitF} !== expected) begin // check result
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$display("Error: PCF = %b, write = %b, data = %b, flush = %b", PCF,
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ITLBWriteF, PageTableEntryF, ITLBFlushF);
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if ({PhysicalAddress, TLBMiss, TLBHit} !== expected) begin // check result
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$display("Error: VirtualAddress = %b, write = %b, data = %b, flush = %b", VirtualAddress,
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TLBWrite, PageTableEntryWrite, TLBFlush);
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$display(" outputs = %b %b %b (%b expected)",
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PCPF, ITLBMissF, ITLBHitF, expected);
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PhysicalAddress, TLBMiss, TLBHit, expected);
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errors = errors + 1;
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end
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vectornum = vectornum + 1;
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@ -24,7 +24,7 @@
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// `include "wally-config.vh"
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`include "wally-config.vh"
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/**
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* sv32 specs
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@ -49,126 +49,159 @@
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/* *** TODO:
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* - add LRU algorithm (select the write index based on which entry was used
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* least recently)
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* - rename signals to use .* notation in CAM and RAM
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*/
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module tlb_toy (
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input clk, reset,
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// The TLB will have 2**ENTRY_BITS total entries
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module tlb_toy #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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// Current value of satp CSR (from privileged unit)
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input [`XLEN-1:0] SATP, // *** How do we get this?
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// Virtual address input
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input [31:0] PCF,
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input [`XLEN-1:0] VirtualAddress,
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// Controls for writing a new entry to the TLB
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input [31:0] PageTableEntryF,
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input ITLBWriteF,
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input [`XLEN-1:0] PageTableEntryWrite,
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input TLBWrite,
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// Invalidate all TLB entries
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input ITLBFlushF,
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input TLBFlush,
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// Physical address outputs
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output [31:0] PCPF,
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output ITLBMissF,
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output ITLBHitF
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output [`XLEN-1:0] PhysicalAddress,
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output TLBMiss,
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output TLBHit
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);
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generate
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if (`XLEN == 32) begin: ARCH
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localparam VPN_BITS = 20;
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localparam PPN_BITS = 22;
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localparam PA_BITS = 34;
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logic SvMode;
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assign SvMode = SATP[31]; // *** change to an enum somehow?
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end else begin: ARCH
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localparam VPN_BITS = 27;
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localparam PPN_BITS = 44;
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localparam PA_BITS = 56;
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logic SvMode; // currently just a boolean whether translation enabled
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assign SvMode = SATP[63]; // *** change to an enum somehow?
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end
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endgenerate
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// Index (currently random) to write the next TLB entry
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logic [2:0] WriteIndexF;
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logic [ENTRY_BITS-1:0] WriteIndex;
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// Sections of the virtual and physical addresses
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logic [19:0] VirtualPageNumberF;
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logic [21:0] PhysicalPageNumberF;
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logic [11:0] PageOffsetF;
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logic [33:0] PhysicalAddressF;
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logic [ARCH.VPN_BITS-1:0] VirtualPageNumber;
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logic [ARCH.PPN_BITS-1:0] PhysicalPageNumber;
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logic [11:0] PageOffset;
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logic [ARCH.PA_BITS-1:0] PhysicalAddressFull;
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// Pattern and pattern location in the CAM
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logic [2:0] VPNIndexF;
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logic [ENTRY_BITS-1:0] VPNIndex;
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// RAM access location
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logic [2:0] ITLBEntryIndex;
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logic [ENTRY_BITS-1:0] EntryIndex;
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// Page table entry matching the virtual address
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logic [31:0] PTEMatchF;
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logic [`XLEN-1:0] PageTableEntry;
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assign VirtualPageNumberF = PCF[31:12];
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assign PageOffsetF = PCF[11:0];
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assign VirtualPageNumber = VirtualAddress[ARCH.VPN_BITS+11:12];
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assign PageOffset = VirtualAddress[11:0];
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// Choose a read or write location to the entry list
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mux2 #(3) indexmux(VPNIndexF, WriteIndexF, ITLBWriteF, ITLBEntryIndex);
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mux2 #(3) indexmux(VPNIndex, WriteIndex, TLBWrite, EntryIndex);
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// Currently use random replacement algorithm
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rand3 rdm(clk, reset, WriteIndexF);
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tlb_rand rdm(.*);
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ram8x32 ram(clk, reset, ITLBEntryIndex, PageTableEntryF, ITLBWriteF, PTEMatchF);
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cam8x21 cam(clk, reset, ITLBWriteF, VirtualPageNumberF, WriteIndexF,
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ITLBFlushF, VPNIndexF, ITLBHitF);
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tlb_ram #(ENTRY_BITS) ram(.*);
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tlb_cam #(ENTRY_BITS, ARCH.VPN_BITS) cam(.*);
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always_comb begin
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assign PhysicalPageNumberF = PTEMatchF[31:10];
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assign PhysicalPageNumber = PageTableEntry[ARCH.PPN_BITS+9:10];
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if (ITLBHitF) begin
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assign PhysicalAddressF = {PhysicalPageNumberF, PageOffsetF};
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if (TLBHit) begin
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assign PhysicalAddressFull = {PhysicalPageNumber, PageOffset};
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end else begin
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assign PhysicalAddressF = 34'b0;
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assign PhysicalAddressFull = 8'b0; // *** Actual behavior; disabled until walker functioning
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//assign PhysicalAddressFull = {2'b0, VirtualPageNumber, PageOffset} // *** pass through should be removed as soon as walker ready
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end
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end
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assign PCPF = PhysicalAddressF[31:0];
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assign ITLBMissF = ~ITLBHitF & ~(ITLBWriteF | ITLBFlushF);
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generate
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if (`XLEN == 32) begin
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mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], ARCH.SvMode, PhysicalAddress);
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end else begin
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mux2 #(`XLEN) addressmux(VirtualAddress, {8'b0, PhysicalAddressFull}, ARCH.SvMode, PhysicalAddress);
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end
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endgenerate
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assign TLBMiss = ~TLBHit & ~(TLBWrite | TLBFlush) & ARCH.SvMode;
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endmodule
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// *** Add parameter for number of tlb lines (currently 8)
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module ram8x32 (
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input clk, reset,
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input [2:0] address,
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input [31:0] data,
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input we,
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module tlb_ram #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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input [ENTRY_BITS-1:0] EntryIndex,
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input [`XLEN-1:0] PageTableEntryWrite,
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input TLBWrite,
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output [31:0] out_data
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output [`XLEN-1:0] PageTableEntry
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);
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logic [31:0] ram [0:7];
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localparam NENTRIES = 2**ENTRY_BITS;
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logic [`XLEN-1:0] ram [0:NENTRIES-1];
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always @(posedge clk) begin
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if (we) ram[address] <= data;
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if (TLBWrite) ram[EntryIndex] <= PageTableEntryWrite;
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end
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assign out_data = ram[address];
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assign PageTableEntry = ram[EntryIndex];
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initial begin
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for (int i = 0; i < 8; i++)
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ram[i] = 32'h0;
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for (int i = 0; i < NENTRIES; i++)
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ram[i] = `XLEN'b0;
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end
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endmodule
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module cam8x21 (
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input clk, reset, we,
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input [19:0] pattern,
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input [2:0] write_address,
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input ITLBFlushF,
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output [2:0] matched_address,
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output match_found
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module tlb_cam #(parameter ENTRY_BITS = 3,
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parameter KEY_BITS = 20) (
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input clk, reset,
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input [KEY_BITS-1:0] VirtualPageNumber,
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input [ENTRY_BITS-1:0] WriteIndex,
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input TLBWrite,
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input TLBFlush,
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output [ENTRY_BITS-1:0] VPNIndex,
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output TLBHit
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);
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logic [20:0] ram [0:7];
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logic [7:0] match_line;
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localparam NENTRIES = 2**ENTRY_BITS;
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logic [2:0] matched_address_comb;
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logic match_found_comb;
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// Each entry of this memory has KEY_BITS for the key plus one valid bit.
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logic [KEY_BITS:0] ram [0:NENTRIES-1];
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logic [ENTRY_BITS-1:0] matched_address_comb;
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logic match_found_comb;
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always @(posedge clk) begin
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if (we) ram[write_address] <= {1'b1,pattern};
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if (ITLBFlushF) begin
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for (int i = 0; i < 8; i++)
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ram[i][20] = 1'b0;
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if (TLBWrite) ram[WriteIndex] <= {1'b1,VirtualPageNumber};
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if (TLBFlush) begin
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for (int i = 0; i < NENTRIES; i++)
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ram[i][KEY_BITS] = 1'b0; // Zero out msb (valid bit) of all entries
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end
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end
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// *** Check whether this for loop synthesizes correctly
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always_comb begin
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match_found_comb = 1'b0;
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matched_address_comb = 3'b0;
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for (int i = 0; i < 8; i++) begin
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if (ram[i] == {1'b1,pattern} && !match_found_comb) begin
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matched_address_comb = '0;
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for (int i = 0; i < NENTRIES; i++) begin
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if (ram[i] == {1'b1,VirtualPageNumber} && !match_found_comb) begin
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matched_address_comb = i;
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match_found_comb = 1;
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end else begin
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@ -178,31 +211,23 @@ module cam8x21 (
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end
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end
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assign matched_address = matched_address_comb;
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assign match_found = match_found_comb & ~(we | ITLBFlushF);
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assign VPNIndex = matched_address_comb;
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assign TLBHit = match_found_comb & ~(TLBWrite | TLBFlush);
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initial begin
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for (int i = 0; i < 8; i++)
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ram[i] <= 0;
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for (int i = 0; i < NENTRIES; i++)
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ram[i] <= '0;
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end
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endmodule
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module mux2 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y);
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assign y = s ? d1 : d0;
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endmodule
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module rand3 (
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module tlb_rand #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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output [2:0] WriteIndexF
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output [ENTRY_BITS:0] WriteIndex
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);
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logic [31:0] data;
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assign data = $urandom;
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assign WriteIndexF = data[2:0];
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assign WriteIndex = data[ENTRY_BITS:0];
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endmodule
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