Revert "Icache now uses physical lenght bits rather than XLEN."

This reverts commit 16266d978a.

wally-pipelined/src/cache/ICacheCntrl.sv

@@ -33,15 +33,15 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
 
     // Input the address to read
     // The upper bits of the physical pc
-    input logic [`PA_BITS-1:0] 	PCNextF,
-    input logic [`PA_BITS-1:0] 	PCPF,
+    input logic [`XLEN-1:0] 	PCNextF,
+    input logic [`XLEN-1:0] 	PCPF,
     // Signals to/from cache memory
     // The read coming out of it
     input logic [31:0] 		ICacheMemReadData,
     input logic 		ICacheMemReadValid,
     // The address at which we want to search the cache memory
-    output logic [`PA_BITS-1:0] 	PCTagF,
-    output logic [`PA_BITS-1:0]    PCNextIndexF,						     
+    output logic [`XLEN-1:0] 	PCTagF,
+    output logic [`XLEN-1:0]    PCNextIndexF,						     
     output logic 		ICacheReadEn,
     // Load data into the cache
     output logic 		ICacheMemWriteEnable,
@@ -133,8 +133,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
   
   logic [LOGWPL:0] 	     FetchCount, NextFetchCount;
 
-  logic [`PA_BITS-1:0] 	     PCPreFinalF, PCPFinalF, PCSpillF;
-  logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF;
+  logic [`XLEN-1:0] 	     PCPreFinalF, PCPFinalF, PCSpillF;
+  logic [`XLEN-1:OFFSETWIDTH] PCPTrunkF;
 
   
   logic [31:0] 		     FinalInstrRawF;
@@ -174,7 +174,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
   assign PCNextIndexF = PCPFinalF;
   
   // truncate the offset from PCPF for memory address generation
-  assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH];
+  assign PCPTrunkF = PCTagF[`XLEN-1:OFFSETWIDTH];
   
     // Detect if the instruction is compressed
   assign CompressedF = FinalInstrRawF[1:0] != 2'b11;

wally-pipelined/src/cache/ICacheMem.sv

@@ -8,8 +8,8 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
    // If flush is high, invalidate the entire cache
    input logic 		       flush,
 
-   input logic [`PA_BITS-1:0]     PCTagF,        // physical address
-   input logic [`PA_BITS-1:0]     PCNextIndexF,  // virtual address
+   input logic [`XLEN-1:0]     PCTagF,        // physical address
+   input logic [`XLEN-1:0]     PCNextIndexF,  // virtual address
    input logic 		       WriteEnable,
    input logic [BLOCKLEN-1:0]  WriteLine,
    output logic [BLOCKLEN-1:0] ReadLineF,
@@ -21,7 +21,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
   localparam OFFSETLEN = $clog2(BLOCKBYTELEN);
   localparam INDEXLEN = $clog2(NUMLINES);
   // *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48
-  localparam TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
+  localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN;
 
   logic [TAGLEN-1:0] 	       LookupTag;
   logic [NUMLINES-1:0] 	       ValidOut;
@@ -39,7 +39,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
   cachetags (.*,
 	     .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	     .ReadData(LookupTag),
-	     .WriteData(PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN])
+	     .WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN])
 	     );
 
   // Correctly handle the valid bits
@@ -55,5 +55,5 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
          end
     DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]];
   end
-  assign HitF = DataValidBit && (LookupTag == PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]);
+  assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]);
 endmodule

wally-pipelined/src/cache/icache.sv

@@ -31,8 +31,8 @@ module icache
    input logic 		    clk, reset,
    input logic 		    StallF, StallD,
    input logic 		    FlushD,
-   input logic [`PA_BITS-1:0]  PCNextF,
-   input logic [`PA_BITS-1:0]  PCPF, 
+   input logic [`XLEN-1:0]  PCNextF,
+   input logic [`XLEN-1:0]  PCPF, 
    // Data read in from the ebu unit
    input logic [`XLEN-1:0]  InstrInF,
    input logic 		    InstrAckF,
@@ -58,7 +58,7 @@ module icache
   logic 		    ICacheMemWriteEnable;
   logic [BLOCKLEN-1:0] 	    ICacheMemWriteData;
   logic 		    EndFetchState;
-  logic [`PA_BITS-1:0] 	    PCTagF, PCNextIndexF;  
+  logic [`XLEN-1:0] 	    PCTagF, PCNextIndexF;  
   // Output signals from cache memory
   logic [31:0] 		    ICacheMemReadData;
   logic 		    ICacheMemReadValid;

wally-pipelined/src/ifu/ifu.sv

@@ -138,9 +138,7 @@ module ifu (
 
   // jarred 2021-03-14 Add instrution cache block to remove rd2
   assign PCNextPF = PCNextF; // Temporary workaround until iTLB is live
-  icache icache(.*,
-		.PCNextF(PCNextF[`PA_BITS-1:0]),
-		.PCPF(PCPFmmu));
+  icache icache(.*);