forked from Github_Repos/cvw
Fixed minor bug in instruction class decoding.
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@ -447,7 +447,14 @@ module icachecontroller #(parameter LINESIZE = 256) (
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// we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros.
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// fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with
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// more zeros after the addition. This will be the number of offset bits less the AHBByteLength.
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assign InstrPAdrF = {{PCPTrunkF, {{LOGWPL}{1'b0}}} + FetchCount, {{OFFSETWIDTH-LOGWPL}{1'b0}}};
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logic [`XLEN-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ;
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assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}};
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assign InstrPAdrTrunkF = PCPTrunkExtF + FetchCount;
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//assign InstrPAdrF = {{PCPTrunkF, {{LOGWPL}{1'b0}}} + FetchCount, {{OFFSETWIDTH-LOGWPL}{1'b0}}};
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assign InstrPAdrF = {InstrPAdrTrunkF, {{OFFSETWIDTH-LOGWPL}{1'b0}}};
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// store read data from memory interface before writing into SRAM.
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@ -210,9 +210,8 @@ module ifu (
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// the branch predictor needs a compact decoding of the instruction class.
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// *** consider adding in the alternate return address x5 for returns.
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assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 && (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
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assign InstrClassD[3] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 5'h01; // return must return to ra or r5
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assign InstrClassD[2] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 4'h01 && (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
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assign InstrClassD[3] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
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assign InstrClassD[2] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 5'h01 && (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
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assign InstrClassD[1] = InstrD[6:0] == 7'h6F && (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5
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assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
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