forked from Github_Repos/cvw
Finish finite state machines for page table walker
This commit is contained in:
Thomas Fleming
parent
7367052e76
commit
e3900bd0fa
@ -48,7 +48,7 @@ module ahblite (
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input logic [1:0] MemSizeM,
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// Signals from MMU
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input logic [`XLEN-1:0] MMUPAdr,
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input logic MMUTranslate,
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input logic MMUTranslate, MMUTranslationComplete,
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output logic [`XLEN-1:0] MMUReadPTE,
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output logic MMUReady,
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// Return from bus
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@ -75,7 +75,8 @@ module ahblite (
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);
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logic GrantData;
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logic [2:0] ISize;
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logic [31:0] AccessAddress;
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logic [2:0] AccessSize, PTESize, ISize;
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logic [`AHBW-1:0] HRDATAMasked, ReadDataM, ReadDataNewW, ReadDataOldW, WriteData;
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logic IReady, DReady;
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logic CaptureDataM;
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@ -89,47 +90,69 @@ module ahblite (
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// Data accesses have priority over instructions. However, if a data access comes
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// while an instruction read is occuring, the instruction read finishes before
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// the data access can take place.
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typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE} statetype;
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typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE, MMUIDLE} statetype;
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statetype BusState, NextBusState;
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flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
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always_comb
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case (BusState)
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IDLE: if (AtomicM[1]) NextBusState = ATOMICREAD;
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else if (MemReadM) NextBusState = MEMREAD; // Memory has pirority over instructions
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else if (MemWriteM) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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ATOMICREAD: if (~HREADY) NextBusState = ATOMICREAD;
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else NextBusState = ATOMICWRITE;
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ATOMICWRITE: if (~HREADY) NextBusState = ATOMICWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMREAD: if (~HREADY) NextBusState = MEMREAD;
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else if (InstrReadF) NextBusState = INSTRREADC;
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else NextBusState = IDLE;
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MEMWRITE: if (~HREADY) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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IDLE: if (MMUTranslate) NextBusState = MMUTRANSLATE;
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else if (AtomicM[1]) NextBusState = ATOMICREAD;
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else if (MemReadM) NextBusState = MEMREAD; // Memory has priority over instructions
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else if (MemWriteM) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MMUTRANSLATE: if (~HREADY) NextBusState = MMUTRANSLATE;
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else NextBusState = MMUIDLE;
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// *** Could the MMUIDLE state just be the normal idle state?
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// Do we trust MMUTranslate to be high exactly when we need translation?
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MMUIDLE: if (~MMUTranslationComplete)
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NextBusState = MMUTRANSLATE;
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else if (AtomicM[1]) NextBusState = ATOMICREAD;
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else if (MemReadM) NextBusState = MEMREAD; // Memory has priority over instructions
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else if (MemWriteM) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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ATOMICREAD: if (~HREADY) NextBusState = ATOMICREAD;
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else NextBusState = ATOMICWRITE;
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ATOMICWRITE: if (~HREADY) NextBusState = ATOMICWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMREAD: if (~HREADY) NextBusState = MEMREAD;
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else if (InstrReadF) NextBusState = INSTRREADC;
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else NextBusState = IDLE;
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MEMWRITE: if (~HREADY) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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INSTRREAD:
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if (~HREADY) NextBusState = INSTRREAD;
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else NextBusState = IDLE; // if (InstrReadF still high)
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INSTRREADC: if (~HREADY) NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage.
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else NextBusState = IDLE;
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if (~HREADY) NextBusState = INSTRREAD;
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else NextBusState = IDLE; // if (InstrReadF still high)
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INSTRREADC: if (~HREADY) NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage.
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else NextBusState = IDLE;
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endcase
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// stall signals
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assign #2 DataStall = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
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(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE);
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assign #1 InstrStall = (NextBusState == INSTRREAD) || (NextBusState == INSTRREADC);
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(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
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(NextBusState == MMUTRANSLATE) || (NextBusState == MMUIDLE);
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// *** Could get finer grained stalling if we distinguish between MMU
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// instruction address translation and data address translation
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assign #1 InstrStall = (NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
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(NextBusState == MMUTRANSLATE) || (NextBusState == MMUIDLE);
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// bus outputs
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assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
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(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE);
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assign #1 HADDR = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0];
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(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE);
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assign #1 AccessAddress = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0];
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assign #1 HADDR = (MMUTranslate) ? MMUPAdr[31:0] : AccessAddress;
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generate
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if (`XLEN == 32) assign PTESize = 3'b010; // in rv32, PTEs are 4 bytes
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else assign PTESize = 3'b011; // in rv64, PTEs are 8 bytes
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endgenerate
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assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
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assign #1 HSIZE = GrantData ? {1'b0, MemSizeM} : ISize;
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assign #1 AccessSize = (GrantData) ? {1'b0, MemSizeM} : ISize;
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assign #1 HSIZE = (MMUTranslate) ? PTESize : AccessSize;
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assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
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@ -145,7 +168,10 @@ module ahblite (
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// Route signals to Instruction and Data Caches
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// *** assumes AHBW = XLEN
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assign #1 MMUReady = (NextBusState == MMUIDLE);
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assign InstrRData = HRDATA;
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assign MMUReadPTE = HRDATA;
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assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
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assign CaptureDataM = ((BusState == MEMREAD) && (NextBusState != MEMREAD)) ||
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((BusState == ATOMICREAD) && (NextBusState == ATOMICWRITE));
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@ -32,25 +32,29 @@ module pagetablewalker (
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input logic [`XLEN-1:0] SATP_REGW,
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input logic MemWriteM,
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input logic ITLBMissF, DTLBMissM,
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input logic [`XLEN-1:0] PCF, MemAdrM,
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output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM,
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output logic ITLBWriteF, DTLBWriteM,
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// *** handshake to tlbs probably not needed, since stalls take effect
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// output logic TranslationComplete
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output logic MMUTranslationComplete,
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// Signals from and to ahblite
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input logic [`XLEN-1:0] MMUReadPTE,
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input logic MMUReady,
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output logic [`XLEN-1:0] MMUPAdr,
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output logic MMUTranslate
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output logic MMUTranslate,
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// Faults
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output logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM
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);
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logic SvMode;
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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logic [`XLEN-1:0] DirectInstrPTE, DirectMemPTE;
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logic [`XLEN-1:0] DirectInstrPTE, DirectMemPTE, TranslationVAdr;
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logic [9:0] DirectPTEFlags = {2'b0, 8'b00001111};
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@ -73,71 +77,233 @@ module pagetablewalker (
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end
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endgenerate
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flopenr #(`XLEN) instrpte(clk, reset, ITLBMissF, DirectInstrPTE, PageTableEntryF);
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flopenr #(`XLEN) datapte(clk, reset, DTLBMissM, DirectMemPTE, PageTableEntryM);
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//flopenr #(`XLEN) instrpte(clk, reset, ITLBMissF, DirectInstrPTE, PageTableEntryF);
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//flopenr #(`XLEN) datapte(clk, reset, DTLBMissM, DirectMemPTE, PageTableEntryM);
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flopr #(1) iwritesignal(clk, reset, ITLBMissF, ITLBWriteF);
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flopr #(1) dwritesignal(clk, reset, DTLBMissM, DTLBWriteM);
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//flopr #(1) iwritesignal(clk, reset, ITLBMissF, ITLBWriteF);
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//flopr #(1) dwritesignal(clk, reset, DTLBMissM, DTLBWriteM);
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// Prefer data address translations over instruction address translations
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assign TranslationVAdr = (DTLBMissM) ? MemAdrM : PCF;
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assign MMUTranslate = DTLBMissM || ITLBMissF;
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/*
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generate
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if (`XLEN == 32) begin
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assign SvMode = SATP_REGW[31];
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logic VPN1 [9:0] = TranslationVAdr[31:22];
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logic VPN0 [9:0] = TranslationVAdr[21:12]; // *** could optimize by not passing offset?
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logic [9:0] VPN1 = TranslationVAdr[31:22];
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logic [9:0] VPN0 = TranslationVAdr[21:12]; // *** could optimize by not passing offset?
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logic TranslationPAdr [33:0];
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logic [33:0] TranslationPAdr;
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logic [21:0] CurrentPPN;
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typedef enum {IDLE, DATA_LEVEL1, DATA_LEVEL0, DATA_LEAF, DATA FAULT} statetype;
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logic Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid;
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logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE;
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typedef enum {IDLE, LEVEL1, LEVEL0, LEAF, FAULT} statetype;
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statetype WalkerState, NextWalkerState;
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) WalkerState <= #1 IDLE;
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else WalkerState <= #1 NextWalkerState;
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// *** Do we need a synchronizer here for walker to talk to ahblite?
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flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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always_comb begin
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NextWalkerState = 'X;
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case (WalkerState)
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IDLE: if (TLBMissM) NextWalkerState = LEVEL1;
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else NextWalkerState = IDLE;
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LEVEL1: if (HREADY && ValidEntry) NextWalkerState = LEVEL0;
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else if (HREADY) NextWalkerState = FAULT;
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else NextWalkerState = LEVEL1;
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LEVEL2: if (HREADY && ValidEntry) NextWalkerState = LEAF;
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else if (HREADY) NextWalkerState = FAULT;
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else NextWalkerState = LEVEL2;
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LEAF: NextWalkerState = IDLE;
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IDLE: if (MMUTranslate) NextWalkerState = LEVEL1;
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else NextWalkerState = IDLE;
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LEVEL1: if (~MMUReady) NextWalkerState = LEVEL1;
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// else if (~ValidPTE || (LeafPTE && BadMegapage))
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// NextWalkerState = FAULT;
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// *** Leave megapage implementation for later
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF;
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else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0;
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else NextWalkerState = FAULT;
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LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0;
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else if (ValidPTE && LeafPTE && ~AccessAlert)
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NextWalkerState = LEAF;
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else NextWalkerState = FAULT;
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LEAF: if (MMUTranslate) NextWalkerState = LEVEL1;
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else NextWalkerState = IDLE;
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FAULT: if (MMUTranslate) NextWalkerState = LEVEL1;
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else NextWalkerState = IDLE;
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endcase
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end
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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// unswizzle PTE bits
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assign {Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid} = MMUReadPTE[7:0];
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// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
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assign MegapageMisaligned = |(CurrentPPN[9:0]);
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid && ~(Writable && ~Readable);
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assign AccessAlert = ~Accessed || (MemWriteM && ~Dirty);
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assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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// *** Should translate this flop block into our flop module notation
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always_ff @(posedge clk, negedge reset)
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if (reset) begin
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TranslationPAdr <= '0;
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PageTableEntryF <= '0;
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TranslationComplete <= '0;
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MMUTranslationComplete <= '0;
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DTLBWriteM <= '0;
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ITLBWriteF <= '0;
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InstrPageFaultM <= '0;
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LoadPageFaultM <= '0;
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StorePageFaultM <= '0;
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end else begin
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// default values
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TranslationPAdr <= '0;
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PageTableEntryF <= '0;
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MMUTranslationComplete <= '0;
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DTLBWriteM <= '0;
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ITLBWriteF <= '0;
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InstrPageFaultM <= '0;
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LoadPageFaultM <= '0;
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StorePageFaultM <= '0;
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case (NextWalkerState)
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LEVEL1: TranslationPAdr <= {BasePageTablePPN, VPN1, 2'b00};
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LEVEL2: TranslationPAdr <= {CurrentPPN, VPN0, 2'b00};
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LEVEL1: begin
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TranslationPAdr <= {BasePageTablePPN, VPN1, 2'b00};
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end
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LEVEL0: begin
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TranslationPAdr <= {CurrentPPN, VPN0, 2'b00};
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end
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LEAF: begin
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PageTableEntryF <= CurrentPageTableEntry;
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TranslationComplete <= '1;
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end
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PageTableEntryF <= MMUReadPTE;
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PageTableEntryM <= MMUReadPTE;
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MMUTranslationComplete <= '1;
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DTLBWriteM <= DTLBMissM;
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ITLBWriteF <= ~DTLBMissM; // Prefer data over instructions
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end
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FAULT: begin
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InstrPageFaultM <= ~DTLBMissM;
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LoadPageFaultM <= DTLBMissM && ~MemWriteM;
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StorePageFaultM <= DTLBMissM && MemWriteM;
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end
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endcase
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end
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assign #1 Translate = (NextWalkerState == LEVEL1);
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// Interpret inputs from ahblite
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assign CurrentPPN = MMUReadPTE[31:10];
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// Assign outputs to ahblite
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// *** Currently truncate address to 32 bits. This must be changed if
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// we support larger physical address spaces
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assign MMUPAdr = TranslationPAdr[31:0];
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end else begin
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// sv39 not yet implemented
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assign SvMode = SATP_REGW[63];
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logic [8:0] VPN2 = TranslationVAdr[38:30];
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logic [8:0] VPN1 = TranslationVAdr[29:21];
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logic [8:0] VPN0 = TranslationVAdr[20:12]; // *** could optimize by not passing offset?
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logic [55:0] TranslationPAdr;
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logic [43:0] CurrentPPN;
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logic Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid;
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logic ValidPTE, AccessAlert, GigapageMisaligned, MegapageMisaligned,
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BadGigapage, BadMegapage, LeafPTE;
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typedef enum {IDLE, LEVEL2, LEVEL1, LEVEL0, LEAF, FAULT} statetype;
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statetype WalkerState, NextWalkerState;
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// *** Do we need a synchronizer here for walker to talk to ahblite?
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flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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always_comb begin
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case (WalkerState)
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IDLE: if (MMUTranslate) NextWalkerState = LEVEL1;
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else NextWalkerState = IDLE;
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LEVEL2: if (~MMUReady) NextWalkerState = LEVEL2;
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else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL1;
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else NextWalkerState = FAULT;
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LEVEL1: if (~MMUReady) NextWalkerState = LEVEL1;
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// else if (~ValidPTE || (LeafPTE && BadMegapage))
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// NextWalkerState = FAULT;
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// *** Leave megapage implementation for later
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF;
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else if (ValidPTE && ~LeafPTE) NextWalkerState = LEVEL0;
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else NextWalkerState = FAULT;
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LEVEL0: if (~MMUReady) NextWalkerState = LEVEL0;
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else if (ValidPTE && LeafPTE && ~AccessAlert)
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NextWalkerState = LEAF;
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else NextWalkerState = FAULT;
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LEAF: if (MMUTranslate) NextWalkerState = LEVEL2;
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else NextWalkerState = IDLE;
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FAULT: if (MMUTranslate) NextWalkerState = LEVEL2;
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else NextWalkerState = IDLE;
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endcase
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end
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// unswizzle PTE bits
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assign {Dirty, Accessed, Global, User,
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Executable, Writable, Readable, Valid} = MMUReadPTE[7:0];
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// A megapage is a Level 1 leaf page. This page must have zero PPN[0].
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assign GigapageMisaligned = |(CurrentPPN[17:0]);
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assign MegapageMisaligned = |(CurrentPPN[8:0]);
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid && ~(Writable && ~Readable);
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assign AccessAlert = ~Accessed || (MemWriteM && ~Dirty);
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assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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// *** Should translate this flop block into our flop module notation
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always_ff @(posedge clk, negedge reset)
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if (reset) begin
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TranslationPAdr <= '0;
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PageTableEntryF <= '0;
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MMUTranslationComplete <= '0;
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DTLBWriteM <= '0;
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ITLBWriteF <= '0;
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InstrPageFaultM <= '0;
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LoadPageFaultM <= '0;
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StorePageFaultM <= '0;
|
||||
end else begin
|
||||
// default values
|
||||
TranslationPAdr <= '0;
|
||||
PageTableEntryF <= '0;
|
||||
MMUTranslationComplete <= '0;
|
||||
DTLBWriteM <= '0;
|
||||
ITLBWriteF <= '0;
|
||||
InstrPageFaultM <= '0;
|
||||
LoadPageFaultM <= '0;
|
||||
StorePageFaultM <= '0;
|
||||
case (NextWalkerState)
|
||||
LEVEL2: begin
|
||||
TranslationPAdr <= {BasePageTablePPN, VPN2, 3'b00};
|
||||
end
|
||||
LEVEL1: begin
|
||||
TranslationPAdr <= {CurrentPPN, VPN1, 3'b00};
|
||||
end
|
||||
LEVEL0: begin
|
||||
TranslationPAdr <= {CurrentPPN, VPN0, 3'b00};
|
||||
end
|
||||
LEAF: begin
|
||||
PageTableEntryF <= MMUReadPTE;
|
||||
PageTableEntryM <= MMUReadPTE;
|
||||
MMUTranslationComplete <= '1;
|
||||
DTLBWriteM <= DTLBMissM;
|
||||
ITLBWriteF <= ~DTLBMissM; // Prefer data over instructions
|
||||
end
|
||||
FAULT: begin
|
||||
InstrPageFaultM <= ~DTLBMissM;
|
||||
LoadPageFaultM <= DTLBMissM && ~MemWriteM;
|
||||
StorePageFaultM <= DTLBMissM && MemWriteM;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// Interpret inputs from ahblite
|
||||
assign CurrentPPN = MMUReadPTE[53:10];
|
||||
|
||||
// Assign outputs to ahblite
|
||||
// *** Currently truncate address to 32 bits. This must be changed if
|
||||
// we support larger physical address spaces
|
||||
assign MMUPAdr = TranslationPAdr[31:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// rv32 case
|
||||
|
||||
|
||||
*/
|
||||
|
||||
endmodule
|
||||
@ -39,6 +39,7 @@ module privileged (
|
||||
input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongM,
|
||||
input logic [3:0] InstrClassM,
|
||||
input logic PrivilegedM,
|
||||
input logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM,
|
||||
input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD,
|
||||
input logic LoadMisalignedFaultM, LoadAccessFaultM,
|
||||
input logic StoreMisalignedFaultM, StoreAccessFaultM,
|
||||
@ -48,7 +49,7 @@ module privileged (
|
||||
output logic [1:0] PrivilegeModeW,
|
||||
output logic [`XLEN-1:0] SATP_REGW,
|
||||
output logic [2:0] FRM_REGW,
|
||||
input logic FlushD, FlushE, FlushM, StallD, StallW
|
||||
input logic FlushD, FlushE, FlushM, StallD, StallW, StallE, StallM
|
||||
);
|
||||
|
||||
logic [1:0] NextPrivilegeModeM;
|
||||
@ -65,7 +66,6 @@ module privileged (
|
||||
logic IllegalInstrFaultM;
|
||||
|
||||
logic BreakpointFaultM, EcallFaultM;
|
||||
logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM;
|
||||
logic MTrapM, STrapM, UTrapM;
|
||||
|
||||
logic [1:0] STATUS_MPP;
|
||||
@ -119,9 +119,11 @@ module privileged (
|
||||
|
||||
assign BreakpointFaultM = ebreakM; // could have other causes too
|
||||
assign EcallFaultM = ecallM;
|
||||
assign InstrPageFaultM = 0;
|
||||
assign LoadPageFaultM = 0;
|
||||
assign StorePageFaultM = 0;
|
||||
// *** Page faults now driven by page table walker. Might need to make the
|
||||
// below signals ORs of a walker fault and a tlb fault if both of those come in
|
||||
// assign InstrPageFaultM = 0;
|
||||
// assign LoadPageFaultM = 0;
|
||||
// assign StorePageFaultM = 0;
|
||||
|
||||
// pipeline fault signals
|
||||
flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
|
||||
|
||||
@ -76,6 +76,7 @@ module wallypipelinedhart (
|
||||
logic InstrMisalignedFaultM;
|
||||
logic DataMisalignedM;
|
||||
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
|
||||
logic InstrPageFaultM, LoadPageFaultM, StorePageFaultM;
|
||||
logic LoadMisalignedFaultM, LoadAccessFaultM;
|
||||
logic StoreMisalignedFaultM, StoreAccessFaultM;
|
||||
logic [`XLEN-1:0] InstrMisalignedAdrM;
|
||||
@ -98,7 +99,7 @@ module wallypipelinedhart (
|
||||
logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM;
|
||||
|
||||
logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
|
||||
logic MMUTranslate, MMUReady;
|
||||
logic MMUTranslate, MMUTranslationComplete, MMUReady;
|
||||
|
||||
// bus interface to dmem
|
||||
logic MemReadM, MemWriteM;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user