Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

The last commit message about rv32ic having issues is now invalid. Looks like the issue was resolved.

wally-pipelined/src/uncore/dtim.sv

@@ -40,6 +40,8 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
   logic [`XLEN-1:0] HREADTim0;
 
 //  logic [`XLEN-1:0] write;
+  logic [31:0] HADDRd;
+  logic        newAdr;
   logic [15:0] entry;
   logic        memread, memwrite;
   logic [3:0]  busycount;
@@ -48,14 +50,17 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
     memread <= HSELTim & ~ HWRITE;
     memwrite <= HSELTim & HWRITE;
     A <= HADDR;
+    HADDRd <= HADDR;
   end
 
+  assign newAdr = HADDR!=HADDRd;
+
   // busy FSM to extend READY signal
   always_ff @(posedge HCLK, negedge HRESETn) 
     if (~HRESETn) begin
       HREADYTim <= 1;
     end else begin
-      if (HREADYTim & HSELTim) begin
+      if ((HREADYTim | newAdr) & HSELTim) begin
         busycount <= 0;
         HREADYTim <= #1 0;
       end else if (~HREADYTim) begin

wally-pipelined/src/uncore/imem.sv

@@ -37,12 +37,12 @@ module imem (
   logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)];
   `endif
  /* verilator lint_on UNDRIVEN */
-  logic [28:0] adrbits;
+  logic [31:0] adrbits; // needs to be 32 bits to index RAM
   logic [`XLEN-1:0] rd;
 //  logic [15:0] rd2;
       
   generate
-    if (`XLEN==32) assign adrbits = AdrF[30:2];
+    if (`XLEN==32) assign adrbits = AdrF[31:2];
     else          assign adrbits = AdrF[31:3];
   endgenerate