Thomas Fleming 53c05d6a73 Clean up lint errors in fpu and muldiv ... booth.sv had an actual error where a signal was being assigned to too many bits. muldiv has a lot of non blocking assignments, so I suppressed those warnings so the linter output was readable.		2021-04-22 15:36:03 -04:00
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bin	Added possibly working OSU test bench as a precursor to running a bp benchmark.	2021-03-17 11:06:32 -05:00
config	greatly improved PLIC register interface	2021-04-22 11:22:01 -04:00
misc/tlb_toy	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	buildroot: sim is now running!	2021-04-17 14:44:32 -04:00
src	Clean up lint errors in fpu and muldiv	2021-04-22 15:36:03 -04:00
testbench	Temporarily disable rv64 mmu test	2021-04-22 13:19:18 -04:00
testgen	Add tests for stval and mtval	2021-04-21 02:31:32 -04:00
lint-wally	Pass lint-wally arguments to verilator	2021-04-22 13:39:20 -04:00