All tests passing with bus interface

wally-pipelined/src/ebu/ahblite.sv

@@ -39,7 +39,7 @@ module ahblite (
   input  logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram
   input  logic             InstrReadF,
 //  input  logic             ResolveBranchD,
-  output logic [31:0] InstrRData,
+  output logic [`XLEN-1:0] InstrRData,
   // Signals from Data Cache
   input  logic [`XLEN-1:0] MemPAdrM,
   input  logic             MemReadM, MemWriteM,
@@ -71,6 +71,7 @@ module ahblite (
   logic [2:0] ISize;
   logic [`AHBW-1:0] HRDATAMasked, ReadDataM, ReadDataPreW;
   logic IReady, DReady;
+  logic CaptureDataM;
 //  logic [3:0] HSIZED; // size delayed by one cycle for reads
 //  logic [2:0] HADDRD; // address delayed for subword reads
 
@@ -139,8 +140,10 @@ module ahblite (
 
     // Route signals to Instruction and Data Caches
   // *** assumes AHBW = XLEN
-  assign InstrRData = HRDATAMasked[31:0];
-//  assign ReadDataW = HRDATAMasked;
+
+  // fix harris 2/24/21 to read all WLEN bits directly for instruction
+  assign InstrRData = HRDATA;
+
   assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
   assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD);
   flopenr #(`XLEN) ReadDataPreWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataPreW); // *** this may break when there is no instruction read after data read

wally-pipelined/src/ifu/ifu.sv

@@ -31,7 +31,7 @@ module ifu (
   input  logic             StallF, StallD, StallE, StallM, StallW,
   input  logic             FlushD, FlushE, FlushM, FlushW,
   // Fetch
-  input  logic [31:0]      InstrF,
+  input  logic [`XLEN-1:0] InstrInF,
   output logic [`XLEN-1:0] PCF, 
   output logic [`XLEN-1:0] InstrPAdrF,
   output logic             InstrReadF,
@@ -53,7 +53,9 @@ module ifu (
   input  logic             IllegalBaseInstrFaultD,
   output logic             IllegalIEUInstrFaultD,
   output logic             InstrMisalignedFaultM,
-  output logic [`XLEN-1:0] InstrMisalignedAdrM
+  output logic [`XLEN-1:0] InstrMisalignedAdrM,
+  // bogus
+  input  logic [15:0] rd2
 );
 
   logic [`XLEN-1:0] UnalignedPCNextF, PCNextF;
@@ -62,7 +64,7 @@ module ifu (
   logic IllegalCompInstrD;
   logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM;
   logic        CompressedF;
-  logic [31:0]     InstrRawD, InstrE, InstrW;
+  logic [31:0]     InstrF, InstrRawD, InstrE, InstrW;
   logic [31:0]     nop = 32'h00000013; // instruction for NOP
 
   // *** put memory interface on here, InstrF becomes output
@@ -94,6 +96,15 @@ module ifu (
       else        PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
     else          PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
 
+  // harris 2/23/21 Add code to fetch instruction split across two words
+  generate 
+    if (`XLEN==32) begin
+      assign InstrF = PCF[1] ? {rd2[15:0], InstrInF[31:16]} : InstrInF;
+    end else begin
+      assign InstrF = PCF[2] ? (PCF[1] ? {rd2[15:0], InstrInF[63:48]} : InstrInF[63:32])
+                          : (PCF[1] ? InstrInF[47:16] : InstrInF[31:0]);
+    end
+  endgenerate
 
   // Decode stage pipeline register and logic
   flopenl #(32)    InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrRawD);

wally-pipelined/src/uncore/imem.sv

@@ -28,6 +28,7 @@
 module imem (
   input  logic [`XLEN-1:1] AdrF,
   output logic [31:0]      InstrF,
+  output logic [15:0]      rd2, // bogus, delete when real multicycle fetch works
   output logic             InstrAccessFaultF);
 
  /* verilator lint_off UNDRIVEN */
@@ -35,7 +36,7 @@ module imem (
  /* verilator lint_on UNDRIVEN */
   logic [15:0] adrbits;
   logic [`XLEN-1:0] rd;
-  logic [15:0] rd2;
+//  logic [15:0] rd2;
       
   generate
     if (`XLEN==32) assign adrbits = AdrF[17:2];

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -35,6 +35,7 @@ module wallypipelinedhart (
   input  logic             InstrAccessFaultF, 
   input  logic             DataAccessFaultM,
   // Bus Interface
+  input  logic [15:0]      rd2, // bogus, delete when real multicycle fetch works
   input  logic [`AHBW-1:0] HRDATA,
   input  logic             HREADY, HRESP,
   output logic             HCLK, HRESETn,
@@ -90,11 +91,12 @@ module wallypipelinedhart (
   logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM;
   logic [`XLEN-1:0] ReadDataW;
   logic [`XLEN-1:0] InstrPAdrF;
+  logic [`XLEN-1:0] InstrRData;
   logic             InstrReadF;
   logic             DataStall, InstrStall;
   logic             InstrAckD, MemAckW;
            
-  ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
+  ifu ifu(.InstrInF(InstrRData), .*); // instruction fetch unit: PC, branch prediction, instruction cache
 
   ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
   dmem dmem(.*); // data cache unit
@@ -102,7 +104,7 @@ module wallypipelinedhart (
 
   ahblite ebu( 
     //.InstrReadF(1'b0),
-    .InstrRData(InstrF), // hook up InstrF later
+    //.InstrRData(InstrF), // hook up InstrF later
     .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
     .*);
 

wally-pipelined/src/wally/wallypipelinedsoc.sv

@@ -67,6 +67,7 @@ module wallypipelinedsoc (
   logic [2:0]       HADDRD;
   logic [3:0]       HSIZED;
   logic             HWRITED;
+  logic [15:0]      rd2; // bogus, delete when real multicycle fetch works
    
   // instantiate processor and memories
   wallypipelinedhart hart(.*);

wally-pipelined/testbench/testbench-imperas.sv

@@ -236,7 +236,7 @@ string tests32i[] = {
   initial 
     if (`XLEN == 64) begin // RV64
       tests = {tests64i};
-      if (`C_SUPPORTED % 2 == 1) tests = {tests64ic, tests};
+      if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic};
       else                       tests = {tests, tests64iNOc};
     end else begin // RV32
       tests = {tests32i};