Removed two cycles of latency from the DTIM

2021-06-10 10:30:24 -04:00 · 2021-06-10 10:30:24 -04:00 · 802238643a
commit 802238643a
parent 3e8026dc21
1 changed files with 1 additions and 1 deletions
--- a/wally-pipelined/src/uncore/dtim.sv
+++ b/wally-pipelined/src/uncore/dtim.sv
@ -69,7 +69,7 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
        busycount <= 0;
        HREADYTim <= #1 0;
      end else if (~HREADYTim) begin
-        if (busycount == 2) begin // TIM latency, for testing purposes.  *** test with different values
+        if (busycount == 0) begin // TIM latency, for testing purposes.  *** test with different values such as 2
          HREADYTim <= #1 1;
        end else begin
          busycount <= busycount + 1;