forked from Github_Repos/cvw
Partial fix to the integer divide stall issue.
This commit is contained in:
Ross Thompson
parent
362f6ea2e6
commit
d21006d048
@ -8,33 +8,42 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/functionRadix/fun
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/InstrStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/InstrStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate /testbench/dut/hart/hzu/StallFCause_Q
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add wave -noupdate /testbench/dut/hart/hzu/StallDCause_Q
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add wave -noupdate /testbench/dut/hart/hzu/StallECause_Q
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add wave -noupdate /testbench/dut/hart/hzu/StallMCause_Q
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add wave -noupdate /testbench/dut/hart/hzu/StallWCause_Q
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add wave -noupdate -group Bpred -expand -group direction -divider Update
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add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdatePC
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add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdateEN
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@ -53,7 +62,6 @@ add wave -noupdate -group Bpred -group BTB -divider Lookup
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
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add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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@ -82,7 +90,6 @@ add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/PCLinkW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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@ -141,8 +148,32 @@ add wave -noupdate -group {function radix debug} /testbench/functionRadix/functi
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrIndex
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add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionName
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/SrcBE
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/Funct3E
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/MulDivE
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/W64E
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/StallM
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/StallW
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/FlushM
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/FlushW
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/MulDivResultW
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/genblk1/div/start
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/DivDoneE
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add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/DivBusyE
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add wave -noupdate /testbench/dut/hart/mdu/genblk1/gclk
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add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
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add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/N
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add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate /testbench/dut/hart/MulDivResultW
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add wave -noupdate /testbench/dut/hart/mdu/genblk1/PrelimResultE
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add wave -noupdate /testbench/dut/hart/mdu/Funct3E
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add wave -noupdate /testbench/dut/hart/mdu/genblk1/QuotE
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {3758805 ns} 0}
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WaveRestoreCursors {{Cursor 2} {128433 ns} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 229
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@ -158,4 +189,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {1644110 ns} {15262484 ns}
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WaveRestoreZoom {128007 ns} {128663 ns}
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@ -26,19 +26,23 @@
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`include "wally-config.vh"
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module hazard(
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input logic clk,
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input logic reset,
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// Detect hazards
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input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
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input logic LoadStallD, MulDivStallD, CSRRdStallD,
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input logic InstrStall, DataStall, ICacheStallF,
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input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
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input logic LoadStallD, MulDivStallD, CSRRdStallD,
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input logic InstrStall, DataStall, ICacheStallF,
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input logic DivBusyE,
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// Stall & flush outputs
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output logic StallF, StallD, StallE, StallM, StallW,
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output logic FlushF, FlushD, FlushE, FlushM, FlushW
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output logic StallF, StallD, StallE, StallM, StallW,
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output logic FlushF, FlushD, FlushE, FlushM, FlushW
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);
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logic BranchFlushDE;
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logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
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logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
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// stalls and flushes
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// loads: stall for one cycle if the subsequent instruction depends on the load
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// branches and jumps: flush the next two instructions if the branch is taken in EXE
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@ -56,9 +60,10 @@ module hazard(
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assign StallFCause = CSRWritePendingDEM & ~(BranchFlushDE);
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assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD) & ~(BranchFlushDE); // stall in decode if instruction is a load/mul/csr dependent on previous
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// assign StallDCause = LoadStallD | MulDivStallD | CSRRdStallD; // stall in decode if instruction is a load/mul/csr dependent on previous
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assign StallECause = 0;
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assign StallECause = DivBusyE;
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assign StallMCause = 0;
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assign StallWCause = DataStall | InstrStall;
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// Each stage stalls if the next stage is stalled or there is a cause to stall this stage.
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assign StallF = StallD | StallFCause;
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@ -68,7 +73,9 @@ module hazard(
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assign StallM = StallW | StallMCause;
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assign StallW = StallWCause;
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//assign FirstUnstalledD = (~StallD & StallF & ~MulDivStallD);
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assign FirstUnstalledD = (~StallD & StallF);
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//assign FirstUnstalledE = (~StallE & StallD & ~MulDivStallD);
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assign FirstUnstalledE = (~StallE & StallD);
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assign FirstUnstalledM = (~StallM & StallE);
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assign FirstUnstalledW = (~StallW & StallM);;
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@ -39,7 +39,7 @@ module muldiv (
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output logic DivDoneE,
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output logic DivBusyE,
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// hazards
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input logic StallM, StallW, FlushM, FlushW
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input logic StallE, StallM, StallW, FlushM, FlushW
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);
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generate
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@ -52,17 +52,39 @@ module muldiv (
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logic DivStartE;
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logic startDivideE;
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logic enable_q, gclk;
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logic [2:0] Funct3E_Q;
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// Multiplier
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mul mul(.*);
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// Divide
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div div (QuotE, RemE, DivDoneE, DivBusyE, div0error, SrcAE, SrcBE, clk, reset, startDivideE);
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// *** replace this clock gater
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always @(~clk) begin
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enable_q <= ~StallM;
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end
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assign gclk = enable_q & clk;
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div div (QuotE, RemE, DivDoneE, DivBusyE, div0error, SrcAE, SrcBE, gclk, reset, startDivideE);
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// Added for debugging of start signal for divide
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assign startDivideE = MulDivE&DivStartE&~DivBusyE;
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// capture the start control signals since they are not held constant.
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flopenrc #(3) funct3ereg (.d(Funct3E),
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.q(Funct3E_Q),
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.en(DivStartE),
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.clear(DivDoneE),
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.reset(reset),
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.clk(clk));
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// Select result
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always_comb
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case (Funct3E)
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// case (DivDoneE ? Funct3E_Q : Funct3E)
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case (Funct3E)
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3'b000: PrelimResultE = ProdE[`XLEN-1:0];
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3'b001: PrelimResultE = ProdE[`XLEN*2-1:`XLEN];
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3'b010: PrelimResultE = ProdE[`XLEN*2-1:`XLEN];
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Block a user