forked from Github_Repos/cvw
Configurable number of performance counters
This commit is contained in:
David Harris
parent
75870a16d7
commit
3e8026dc21
@ -35,7 +35,7 @@
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// MISA RISC-V configuration per specification
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`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define ZCSR_SUPPORTED 1
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31
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`define COUNTERS 32
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`define ZCOUNTERS_SUPPORTED 1
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// Microarchitectural Features
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@ -1,3 +1,285 @@
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///////////////////////////////////////////
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// csrc.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Counter CSRs
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// See RISC-V Privileged Mode Specification 20190608 3.1.10-11
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module csrc #(parameter
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MCYCLE = 12'hB00,
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// MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive
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// MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT
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MINSTRET = 12'hB02,
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MHPMCOUNTERBASE = 12'hB00,
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//MHPMCOUNTER3 = 12'hB03,
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//MHPMCOUNTER4 = 12'hB04,
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// ... more counters
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//MHPMCOUNTER31 = 12'hB1F,
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MCYCLEH = 12'hB80,
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// MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive
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// MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT
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MINSTRETH = 12'hB82,
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MHPMCOUNTERHBASE = 12'hB80,
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//MHPMCOUNTER3H = 12'hB83,
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//MHPMCOUNTER4H = 12'hB84,
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// ... more counters
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//MHPMCOUNTER31H = 12'hB9F,
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MCOUNTERINHIBIT = 12'h320,
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MHPMEVENTBASE = 12'h320,
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//MHPMEVENT3 = 12'h323,
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//MHPMEVENT4 = 12'h324,
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// ... more counters
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//MHPMEVENT31 = 12'h33F,
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CYCLE = 12'hC00,
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// TIME = 12'hC01, // not specified
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INSTRET = 12'hC02,
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HPMCOUNTERBASE = 12'hC00,
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//HPMCOUNTER3 = 12'hC03,
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//HPMCOUNTER4 = 12'hC04,
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// ...more counters
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//HPMCOUNTER31 = 12'hC1F,
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CYCLEH = 12'hC80,
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// TIMEH = 12'hC81, // not specified
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INSTRETH = 12'hC82,
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HPMCOUNTERHBASE = 12'hC80
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//HPMCOUNTER3H = 12'hC83,
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//HPMCOUNTER4H = 12'hC84,
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// ... more counters
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//HPMCOUNTER31H = 12'hC9F
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) (
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input logic clk, reset,
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input logic InstrValidW, LoadStallD, CSRMWriteM,
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input logic [11:0] CSRAdrM,
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
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output logic [`XLEN-1:0] CSRCReadValM,
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output logic IllegalCSRCAccessM
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);
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generate
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if (`ZCOUNTERS_SUPPORTED) begin
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// logic [63:0] TIME_REGW, TIMECMP_REGW;
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logic [63:0] CYCLE_REGW, INSTRET_REGW;
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logic [63:0] HPMCOUNTER3_REGW, HPMCOUNTER4_REGW; // add more performance counters here if desired
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logic [63:0] CYCLEPlusM, INSTRETPlusM;
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logic [63:0] HPMCOUNTER3PlusM, HPMCOUNTER4PlusM;
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// logic [`XLEN-1:0] NextTIMEM;
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logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
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logic [`XLEN-1:0] NextHPMCOUNTER3M, NextHPMCOUNTER4M;
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logic WriteCYCLEM, WriteINSTRETM;
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logic WriteHPMCOUNTER3M, WriteHPMCOUNTER4M;
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logic [4:0] CounterNumM;
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logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTER_REGW, HPMCOUNTERH_REGW;
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//logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTERH_REGW;
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// Write enables
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// assign WriteTIMEM = CSRMWriteM && (CSRAdrM == MTIME);
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// assign WriteTIMECMPM = CSRMWriteM && (CSRAdrM == MTIMECMP);
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assign WriteCYCLEM = CSRMWriteM && (CSRAdrM == MCYCLE);
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assign WriteINSTRETM = CSRMWriteM && (CSRAdrM == MINSTRET);
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//assign WriteHPMCOUNTER3M = CSRMWriteM && (CSRAdrM == MHPMCOUNTER3);
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//assign WriteHPMCOUNTER4M = CSRMWriteM && (CSRAdrM == MHPMCOUNTER4);
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// Counter adders with inhibits for power savings
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assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]};
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// assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited
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assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~MCOUNTINHIBIT_REGW[2]};
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//assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls
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///assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
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assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0];
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// assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0];
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assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[`XLEN-1:0];
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//assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[`XLEN-1:0];
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//assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[`XLEN-1:0];
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// parameterized number of additional counters
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if (`COUNTERS > 3) begin
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logic [`COUNTERS-1:3] WriteHPMCOUNTERM, CounterEvent;
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logic [63:0] /*HPMCOUNTER_REGW[`COUNTERS-1:3], */ HPMCOUNTERPlusM[`COUNTERS-1:3];
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logic [`XLEN-1:0] NextHPMCOUNTERM[`COUNTERS-1:3];
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genvar i;
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assign CounterEvent[3] = LoadStallD;
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assign CounterEvent[`COUNTERS-1:4] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
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for (i = 3; i < `COUNTERS; i = i+1) begin
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assign WriteHPMCOUNTERM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERBASE + i);
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assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
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always @(posedge clk, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
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else HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
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//flopr #(`XLEN) HPMCOUNTERreg[i](clk, reset, NextHPMCOUNTERM[i], HPMCOUNTER_REGW[i]);
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if (`XLEN==32) begin
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logic [`COUNTERS-1:3] WriteHPMCOUNTERHM;
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logic [`XLEN-1:0] NextHPMCOUNTERHM[`COUNTERS-1:3];
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assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
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assign WriteHPMCOUNTERHM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERHBASE + i);
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assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
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always @(posedge clk, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
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else HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
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//flopr #(`XLEN) HPMCOUNTERHreg[i](clk, reset, NextHPMCOUNTERHM[i], HPMCOUNTER_REGW[i][63:32]);
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end else begin
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assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
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end
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end
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end
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// Write / update counters
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// Only the Machine mode versions of the counter CSRs are writable
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if (`XLEN==64) begin// 64-bit counters
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// flopr #(64) TIMEreg(clk, reset, WriteTIMEM ? CSRWriteValM : TIME_REGW + 1, TIME_REGW); // may count off a different clock***
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// flopenr #(64) TIMECMPreg(clk, reset, WriteTIMECMPM, CSRWriteValM, TIMECMP_REGW);
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flopr #(64) CYCLEreg(clk, reset, NextCYCLEM, CYCLE_REGW);
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flopr #(64) INSTRETreg(clk, reset, NextINSTRETM, INSTRET_REGW);
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//flopr #(64) HPMCOUNTER3reg(clk, reset, NextHPMCOUNTER3M, HPMCOUNTER3_REGW);
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//flopr #(64) HPMCOUNTER4reg(clk, reset, NextHPMCOUNTER4M, HPMCOUNTER4_REGW);
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end else begin // 32-bit low and high counters
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logic WriteTIMEHM, WriteTIMECMPHM, WriteCYCLEHM, WriteINSTRETHM;
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//logic WriteHPMCOUNTER3HM, WriteHPMCOUNTER4HM;
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logic [`XLEN-1:0] NextCYCLEHM, NextTIMEHM, NextINSTRETHM;
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//logic [`XLEN-1:0] NextHPMCOUNTER3HM, NextHPMCOUNTER4HM;
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// Write Enables
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// assign WriteTIMEHM = CSRMWriteM && (CSRAdrM == MTIMEH);
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// assign WriteTIMECMPHM = CSRMWriteM && (CSRAdrM == MTIMECMPH);
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assign WriteCYCLEHM = CSRMWriteM && (CSRAdrM == MCYCLEH);
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assign WriteINSTRETHM = CSRMWriteM && (CSRAdrM == MINSTRETH);
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//assign WriteHPMCOUNTER3HM = CSRMWriteM && (CSRAdrM == MHPMCOUNTER3H);
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//assign WriteHPMCOUNTER4HM = CSRMWriteM && (CSRAdrM == MHPMCOUNTER4H);
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assign NextCYCLEHM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[63:32];
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// assign NextTIMEHM = WriteTIMEHM ? CSRWriteValM : TIMEPlusM[63:32];
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assign NextINSTRETHM = WriteINSTRETHM ? CSRWriteValM : INSTRETPlusM[63:32];
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//assign NextHPMCOUNTER3HM = WriteHPMCOUNTER3HM ? CSRWriteValM : HPMCOUNTER3PlusM[63:32];
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//assign NextHPMCOUNTER4HM = WriteHPMCOUNTER4HM ? CSRWriteValM : HPMCOUNTER4PlusM[63:32];
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// Counter CSRs
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// flopr #(32) TIMEreg(clk, reset, NextTIMEM, TIME_REGW); // may count off a different clock***
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// flopenr #(32) TIMECMPreg(clk, reset, WriteTIMECMPM, CSRWriteValM, TIMECMP_REGW[31:0]);
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flopr #(32) CYCLEreg(clk, reset, NextCYCLEM, CYCLE_REGW[31:0]);
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flopr #(32) INSTRETreg(clk, reset, NextINSTRETM, INSTRET_REGW[31:0]);
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//flopr #(32) HPMCOUNTER3reg(clk, reset, NextHPMCOUNTER3M, HPMCOUNTER3_REGW[31:0]);
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//flopr #(32) HPMCOUNTER4reg(clk, reset, NextHPMCOUNTER4M, HPMCOUNTER4_REGW[31:0]);
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// flopr #(32) TIMEHreg(clk, reset, NextTIMEHM, TIME_REGW); // may count off a different clock***
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// flopenr #(32) TIMECMPHreg(clk, reset, WriteTIMECMPHM, CSRWriteValM, TIMECMP_REGW[63:32]);
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flopr #(32) CYCLEHreg(clk, reset, NextCYCLEHM, CYCLE_REGW[63:32]);
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flopr #(32) INSTRETHreg(clk, reset, NextINSTRETHM, INSTRET_REGW[63:32]);
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//flopr #(32) HPMCOUNTER3Hreg(clk, reset, NextHPMCOUNTER3HM, HPMCOUNTER3_REGW[63:32]);
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//flopr #(32) HPMCOUNTER4Hreg(clk, reset, NextHPMCOUNTER4HM, HPMCOUNTER4_REGW[63:32]);
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end
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// eventually move TIME and TIMECMP to the CLINT
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// run TIME off asynchronous reference clock
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// synchronize write enable to TIME
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// four phase handshake to synchronize reads from TIME
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// interrupt on timer compare
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// ability to disable optional CSRs
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// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
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assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
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if (`XLEN==64) // 64-bit counter reads
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always_comb
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if (PrivilegeModeW == `M_MODE ||
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MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
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IllegalCSRCAccessM = 0;
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if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE];
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else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE];
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else case (CSRAdrM)
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// MTIME: CSRCReadValM = TIME_REGW;
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// MTIMECMP: CSRCReadValM = TIMECMP_REGW;
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MCYCLE: CSRCReadValM = CYCLE_REGW;
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MINSTRET: CSRCReadValM = INSTRET_REGW;
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//MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW;
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//MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW;
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// TIME: CSRCReadValM = TIME_REGW;
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CYCLE: CSRCReadValM = CYCLE_REGW;
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INSTRET: CSRCReadValM = INSTRET_REGW;
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//HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW;
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//HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW;
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default: begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1;
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end
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endcase
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end else begin
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IllegalCSRCAccessM = 1; // no privileges for this csr
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CSRCReadValM = 0;
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end
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else // 32-bit counter reads
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always_comb
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if (PrivilegeModeW == `M_MODE || MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
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IllegalCSRCAccessM = 0;
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if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE];
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else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE];
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else if (CSRAdrM >= MHPMCOUNTERHBASE+3 && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-MHPMCOUNTERHBASE];
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else if (CSRAdrM >= HPMCOUNTERHBASE+3 && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-HPMCOUNTERHBASE];
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else case (CSRAdrM)
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// MTIME: CSRCReadValM = TIME_REGW[31:0];
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// MTIMECMP: CSRCReadValM = TIMECMP_REGW[31:0];
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MCYCLE: CSRCReadValM = CYCLE_REGW[31:0];
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MINSTRET: CSRCReadValM = INSTRET_REGW[31:0];
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//MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0];
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//MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0];
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// TIME: CSRCReadValM = TIME_REGW[31:0];
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CYCLE: CSRCReadValM = CYCLE_REGW[31:0];
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INSTRET: CSRCReadValM = INSTRET_REGW[31:0];
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//HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0];
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//HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0];
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// MTIMEH: CSRCReadValM = TIME_REGW[63:32];
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// MTIMECMPH: CSRCReadValM = TIMECMP_REGW[63:32];
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MCYCLEH: CSRCReadValM = CYCLE_REGW[63:32];
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MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32];
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//MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32];
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//MHPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32];
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// TIMEH: CSRCReadValM = TIME_REGW[63:32];
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CYCLEH: CSRCReadValM = CYCLE_REGW[63:32];
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INSTRETH: CSRCReadValM = INSTRET_REGW[63:32];
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//HPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32];
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//HPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32];
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default: begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1;
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end
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endcase
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end else begin
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IllegalCSRCAccessM = 1; // no privileges for this csr
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CSRCReadValM = 0;
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end
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end else begin
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assign CSRCReadValM = 0;
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assign IllegalCSRCAccessM = 1;
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end
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endgenerate
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endmodule
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/* Bad code from class
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///////////////////////////////////////////
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// csrc.sv
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//
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@ -29,8 +311,14 @@
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`include "wally-config.vh"
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module csrc (
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input logic clk, reset,
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module csrc #(parameter
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// counters
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MHPMCOUNTERBASE = 12'hB00,
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MHPMCOUNTERHBASE = 12'hB80,
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MPHMEVENTBASE = 12'h320,
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HPMCOUNTERBASE = 12'hC00,
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HPMCOUNTERHBASE = 12'hC80,
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)(input logic clk, reset,
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input logic StallD, StallE, StallM, StallW,
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input logic InstrValidW, LoadStallD, CSRMWriteM,
|
||||
input logic BPPredDirWrongM,
|
||||
@ -45,6 +333,9 @@ module csrc (
|
||||
output logic [`XLEN-1:0] CSRCReadValM,
|
||||
output logic IllegalCSRCAccessM);
|
||||
|
||||
// counters
|
||||
|
||||
|
||||
// create Counter arrays to store address of each counter
|
||||
integer MHPMCOUNTER [`COUNTERS:0];
|
||||
integer MHPMCOUNTERH [`COUNTERS:0];
|
||||
@ -199,4 +490,4 @@ module csrc (
|
||||
end // end for else
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
*/
|
||||
Loading…
Reference in New Issue
Block a user