Shriya Nadgauda c66e63ff70 adding pipeline testing		2021-04-23 14:19:17 -04:00
..
bin	Added possibly working OSU test bench as a precursor to running a bp benchmark.	2021-03-17 11:06:32 -05:00
config	greatly improved PLIC register interface	2021-04-22 11:22:01 -04:00
misc/tlb_toy	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Remind people to run make allclean when a regression fails	2021-04-22 19:21:00 -04:00
src	Write PCM to TVAL registers	2021-04-22 16:17:57 -04:00
testbench	adding pipeline testing	2021-04-23 14:19:17 -04:00
testgen	adding pipeline testing	2021-04-23 14:19:17 -04:00
lint-wally	Pass lint-wally arguments to verilator	2021-04-22 13:39:20 -04:00