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Restructured TLB Read as AND-OR operation with one-hot match/read line

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This commit is contained in:
David Harris 2021-07-04 17:01:22 -04:00
parent 8337d6df68
commit 07ef67e537
5 changed files with 55 additions and 58 deletions
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9
wally-pipelined/src/mmu/tlbcam.sv
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@ -45,8 +45,7 @@ module tlbcam #(parameter ENTRY_BITS = 3,
localparam NENTRIES = 2**ENTRY_BITS;
logic [1:0] PageTypeList [NENTRIES-1:0];
logic [1:0] PageTypeRead [NENTRIES-1:0];
logic [NENTRIES-1:0] Matches;
// Create NENTRIES CAM lines, each of which will independently consider
@ -56,8 +55,8 @@ module tlbcam #(parameter ENTRY_BITS = 3,
// page number segments.
tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[NENTRIES-1:0](
.CAMLineWrite(WriteEnables),
.MatchedPageType(PageTypeList), // *** change name to agree
.WriteEnable(WriteEnables),
.PageTypeRead, // *** change name to agree
.Match(ReadLines), // *** change name to agree
.*);
@ -67,6 +66,6 @@ module tlbcam #(parameter ENTRY_BITS = 3,
//priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex);
assign CAMHit = |ReadLines & ~TLBFlush;
assign HitPageType = PageTypeList.or; // applies OR to elements of the (NENTRIES x 2) array to get 2-bit result
assign HitPageType = PageTypeRead.or; // applies OR to elements of the (NENTRIES x 2) array to get 2-bit result
endmodule

16
wally-pipelined/src/mmu/tlbcamline.sv
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@ -39,7 +39,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
input logic [KEY_BITS-1:0] VirtualPageNumber,
// Signals to write a new entry to this line
input logic CAMLineWrite,
input logic WriteEnable,
input logic [1:0] PageTypeWriteVal,
// Flush this line (set valid to 0)
@ -50,7 +50,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
// PageType == 2'b01 --> megapage
// PageType == 2'b10 --> gigapage
// PageType == 2'b11 --> terapage
output logic [1:0] MatchedPageType, // *** should this be the stored version or the always updated one?
output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one?
output logic Match
);
@ -59,11 +59,12 @@ module tlbcamline #(parameter KEY_BITS = 20,
logic [KEY_BITS-1:0] Key;
logic [1:0] PageType;
// Split up key and query into sections for each page table level.
logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
logic Match0, Match1;
// *** need to add ASID and G bit support
generate
if (`XLEN == 32) begin
@ -98,15 +99,14 @@ module tlbcamline #(parameter KEY_BITS = 20,
endgenerate
// On a write, update the type of the page referred to by this line.
flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWriteVal, PageType);
assign MatchedPageType = PageType & {2{Match}};
//mux2 #(2) pagetypemux(StoredPageType, PageTypeWrite, CAMLineWrite, PageType);
flopenr #(2) pagetypeflop(clk, reset, WriteEnable, PageTypeWriteVal, PageType);
assign PageTypeRead = PageType & {2{Match}};
// On a write, set the valid bit high and update the stored key.
// On a flush, zero the valid bit and leave the key unchanged.
// *** Might we want to update stored key right away to output match on the
// write cycle? (using a mux)
flopenrc #(1) validbitflop(clk, reset, TLBFlush, CAMLineWrite, 1'b1, Valid);
flopenr #(KEY_BITS) keyflop(clk, reset, CAMLineWrite, VirtualPageNumber, Key);
flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, VirtualPageNumber, Key);
endmodule

19
wally-pipelined/src/mmu/tlblru.sv
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@ -44,25 +44,14 @@ module tlblru #(parameter ENTRY_BITS = 3) (
// High if the next access causes all RU bits to be 1
logic AllUsed;
// Convert indices to one-hot encodings
//decoder #(ENTRY_BITS) readdecoder(VPNIndex, ReadLineOneHot);
// Find the first line not recently used
tlbpriority #(NENTRIES) nru(~RUBits, WriteLines);
//priorityencoder #(ENTRY_BITS) firstnru(~RUBits, WriteIndex);
// Access either the hit line or written line
// Track recently used lines, updating on a CAM Hit or TLB write
assign AccessLines = TLBWrite ? WriteLines : ReadLines;
// Raise the bit of the recently accessed line
assign RUBitsAccessed = AccessLines | RUBits;
// Determine whether we need to reset the RU bits to all zeroes
assign AllUsed = &RUBitsAccessed;
assign RUBitsNext = AllUsed ? AccessLines : RUBitsAccessed; // *** seems it should set to 0, not to AccessLines
// Update LRU state on any TLB hit or write
flopenrc #(NENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite),
RUBitsNext, RUBits);
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
flopenrc #(NENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits);
endmodule

31
wally-pipelined/src/mmu/tlbram.sv
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@ -41,42 +41,13 @@ module tlbram #(parameter ENTRY_BITS = 3) (
localparam NENTRIES = 2**ENTRY_BITS;
//logic [`XLEN-1:0] ram[NENTRIES-1:0];
logic [`XLEN-1:0] RamRead[NENTRIES-1:0];
logic [`XLEN-1:0] PageTableEntry;
// logic [ENTRY_BITS-1:0] VPNIndex;
// Generate a flop for every entry in the RAM
//flopenr #(`XLEN) pteflops[NENTRIES-1:0](clk, reset, WriteEnables, PTEWriteVal, ram);
tlbramline #(`XLEN) tlblineram[NENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead);
/*
// temporary code for read
// verilator lint_off WIDTH
integer i;
generate
always_comb begin
VPNIndex = 0;
for (i=0; i<NENTRIES; i++)
if (ReadLines[i]) VPNIndex = i;
end
endgenerate
// verilator lint_on WIDTH
*/
//assign PageTableEntry = ram[VPNIndex]; // *** need to fix
assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
assign PTEAccessBits = PageTableEntry[7:0];
assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10];
endmodule
module tlbramline #(parameter WIDTH)
(input logic clk, reset,
input logic re, we,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
logic [WIDTH-1:0] line;
flopenr #(`XLEN) pteflop(clk, reset, we, d, line);
assign q = re ? line : 0;
endmodule

38
wally-pipelined/src/mmu/tlbramline.sv Normal file
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@ -0,0 +1,38 @@
///////////////////////////////////////////
// tlbramline.sv
//
// Written: David_Harris@hmc.edu 4 July 2021
// Modified:
//
// Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module tlbramline #(parameter WIDTH)
(input logic clk, reset,
input logic re, we,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
logic [WIDTH-1:0] line;
flopenr #(`XLEN) pteflop(clk, reset, we, d, line);
assign q = re ? line : 0;
endmodule