forked from Github_Repos/cvw
Commented out some unused modules
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David Harris
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e90c532258
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@ -2,6 +2,7 @@
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// It is unsigned and uses Radix-4 Booth encoding.
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// This file was automatically generated by tdm.pl.
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/*
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module mult64 (x, y, P);
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input [63:0] x;
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@ -18,7 +19,8 @@ module mult64 (x, y, P);
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//assign P = Pt[127:0];
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ldf128 cpa (cout, P, Sum, Carry, 1'b0);
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endmodule // mult64
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endmodule // mult64
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*/
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module multiplier( y, x, Sum, Carry );
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@ -11612,7 +11614,7 @@ module r4be(x0,x1,x2,sing,doub,neg);
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endmodule // r4be
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/*
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// Use maj and two xor2's, with cin being late
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module fullAdd_xc(cout, s, a, b, cin);
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@ -11629,7 +11631,7 @@ module fullAdd_xc(cout, s, a, b, cin);
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maj MAJ_0_112(cout,a,b,cin);
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endmodule // fullAdd_xc
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*/
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module maj(y, a, b, c);
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@ -11645,6 +11647,7 @@ module maj(y, a, b, c);
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endmodule // maj
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/*
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// 4:2 Weinberger compressor
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module fourtwo_x(t, S, C, X, Y, Z, W, t_1);
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@ -11664,6 +11667,7 @@ module fourtwo_x(t, S, C, X, Y, Z, W, t_1);
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fullAdd_xc secondCSA_0_160(C,S,W,t_1,intermediate);
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endmodule // fourtwo_x
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*/
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module inverter(egress, in);
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@ -11767,6 +11771,7 @@ module fullAdd_x(cout,sum,a,b,c);
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endmodule // fullAdd_x
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/*
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module nand2(egress,in1,in2);
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output egress;
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@ -11800,7 +11805,7 @@ module and3(y,a,b,c);
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assign y = a&b&c;
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endmodule // and3
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*/
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module and2(y,a,b);
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output y;
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@ -11810,7 +11815,7 @@ module and2(y,a,b);
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assign y = a&b;
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endmodule // and2
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/*
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module nor2(egress,in1,in2);
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output egress;
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@ -11902,6 +11907,7 @@ module oai(egress,in1,in2,in3);
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assign egress = ~(in3 & (in1|in2));
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endmodule // oai
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*/
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module aoi(egress,in1,in2,in3);
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@ -11949,7 +11955,7 @@ module fullAdd_i(cout_b,sum_b,a,b,c);
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sum_b sum_0_32(sum_b,a,b,c,cout_b);
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endmodule // fullAdd_i
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/*
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module fullAdd(cout,s,a,b,c);
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output cout;
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@ -11979,7 +11985,7 @@ module blackCell(g_i_j, p_i_j, g_i_k, p_i_k, g_kneg1_j, p_kneg1_j);
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and2 and_0_48(p_i_j, p_i_k, p_kneg1_j);
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endmodule // blackCell
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*/
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module grayCell(g_i_j, g_i_k, p_i_k, g_kneg1_j);
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output g_i_j;
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@ -118,6 +118,7 @@ module barrel_shifter_r57 (Z, Sticky, A, Shift);
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endmodule // barrel_shifter_r57
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/*
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module barrel_shifter_r64 (Z, Sticky, A, Shift);
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input [63:0] A;
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@ -160,3 +161,4 @@ module barrel_shifter_r64 (Z, Sticky, A, Shift);
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assign Sticky = (S != sixtythreezeros);
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endmodule // barrel_shifter_r64
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*/
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@ -307,7 +307,7 @@ module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c,
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assign carry = {carry_temp[WIDTH-1:1], 1'b0};
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endmodule // csa
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/*
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module eqcmp #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] a, b,
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output logic y);
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@ -315,6 +315,7 @@ module eqcmp #(parameter WIDTH = 8)
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assign y = (a == b);
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endmodule // eqcmp
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*/
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// QST for r=4
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module qst4 (input logic [6:0] s, input logic [2:0] d,
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@ -1,71 +0,0 @@
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///////////////////////////////////////////
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// imem.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose:
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module imem (
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input logic [`XLEN-1:1] AdrF,
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output logic [31:0] InstrF,
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output logic [15:0] rd2, // bogus, delete when real multicycle fetch works
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output logic InstrAccessFaultF);
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/* verilator lint_off UNDRIVEN */
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logic [`XLEN-1:0] RAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>(1+`XLEN/32)];
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logic [`XLEN-1:0] bootram[`BOOTTIM_BASE>>(1+`XLEN/32):(`BOOTTIM_RANGE+`BOOTTIM_BASE)>>(1+`XLEN/32)];
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/* verilator lint_on UNDRIVEN */
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logic [31:0] adrbits; // needs to be 32 bits to index RAM
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logic [`XLEN-1:0] rd;
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// logic [15:0] rd2;
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generate
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if (`XLEN==32) assign adrbits = AdrF[31:2];
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else assign adrbits = AdrF[31:3];
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endgenerate
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assign #2 rd = (AdrF < (`TIM_BASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options
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// hack right now for unaligned 32-bit instructions
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// eventually this will need to cause a stall like a cache miss
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// when the instruction wraps around a cache line
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// could be optimized to only stall when the instruction wrapping is 32 bits
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assign #2 rd2 = (AdrF < (`TIM_BASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options
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generate
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if (`XLEN==32) begin
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assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd;
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// First, AdrF needs to get its last bit appended back onto it
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// Then not-XORing it with TIM_BASE checks if it matches TIM_BASE exactly
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// Then ORing it with TIM_RANGE introduces some leeway into the previous check, by allowing the lower bits to be either high or low
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assign InstrAccessFaultF = (~&(({AdrF,1'b0} ~^ `TIM_BASE) | `TIM_RANGE)) & (~&(({AdrF,1'b0} ~^ `BOOTTIM_BASE) | `BOOTTIM_RANGE));
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end else begin
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assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32])
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: (AdrF[1] ? rd[47:16] : rd[31:0]);
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//
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assign InstrAccessFaultF = (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIM_BASE | `TIM_RANGE)) & (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `BOOTTIM_BASE | `BOOTTIM_RANGE));
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end
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endgenerate
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endmodule
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