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adapted coremark bare testbench to new dtim RAM HDL

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This commit is contained in:
Teo Ene 2021-03-17 16:59:02 -05:00
parent 4fd0ecff69
commit d2fe42d6d0
1 changed files with 1 additions and 1 deletions
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wally-pipelined/testbench/testbench-coremark_bare.sv
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@ -74,7 +74,7 @@ module testbench();
memfilename = tests[0];
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
for(j=2371; j < 65535; j = j+1)
for(j=268437829; j < 268566528; j = j+1)
dut.uncore.dtim.RAM[j] = 64'b0;
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr";
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab";