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busybear: use (slightly) less terrible verilog

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This commit is contained in:
Noah Boorstin 2021-04-14 00:18:44 -04:00
parent c75455cc41
commit d66fcbc4ab
1 changed files with 3 additions and 6 deletions
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9
wally-pipelined/testbench/testbench-busybear.sv
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@ -279,18 +279,15 @@ module testbench_busybear();
end
end
function logic icmp(string x, y);
return x.icompare(y);
endfunction
`define CHECK_CSR2(CSR, PATH) \
string CSR; \
logic [63:0] expected``CSR``; \
//CSR checking \
always @(``PATH``.``CSR``_REGW) begin \
if ($time > 1) begin \
if (icmp("SEPC", `"CSR`")) begin #1; end \
if (icmp("SCAUSE", `"CSR`")) begin #2; end \
if (icmp("SSTATUS", `"CSR`")) begin #3; end \
if ("SEPC" == `"CSR`") begin #1; end \
if ("SCAUSE" == `"CSR`") begin #2; end \
if ("SSTATUS" == `"CSR`") begin #3; end \
scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
if(CSR.icompare(`"CSR`")) begin \