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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR

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This commit is contained in:
bbracker 2021-06-20 22:38:25 -04:00
parent bf3c2dc089
commit 23f479d225
11 changed files with 2 additions and 29 deletions
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3
wally-pipelined/config/buildroot/wally-config.vh
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@ -90,9 +90,6 @@
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 0
// Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0
// Hardware configuration
`define UART_PRESCALE 1

3
wally-pipelined/config/busybear/wally-config.vh
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@ -91,9 +91,6 @@
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 0
// Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 1
// Hardware configuration
//`define UART_PRESCALE 1
`define UART_PRESCALE 0

3
wally-pipelined/config/coremark/wally-config.vh
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@ -88,9 +88,6 @@
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 0
// Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0
// Hardware configuration
`define UART_PRESCALE 1

3
wally-pipelined/config/coremark_bare/wally-config.vh
View File

@ -91,9 +91,6 @@
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 1
// Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0
// Hardware configuration
`define UART_PRESCALE 1

3
wally-pipelined/config/rv32ic/wally-config.vh
View File

@ -90,9 +90,6 @@
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 1
// Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0
// Hardware configuration
`define UART_PRESCALE 1

3
wally-pipelined/config/rv64BP/wally-config.vh
View File

@ -89,9 +89,6 @@
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 1
// Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0
// Hardware configuration
`define UART_PRESCALE 1

3
wally-pipelined/config/rv64ic/wally-config.vh
View File

@ -91,9 +91,6 @@
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 1
// Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0
// Hardware configuration
`define UART_PRESCALE 1

3
wally-pipelined/config/rv64icfd/wally-config.vh
View File

@ -91,9 +91,6 @@
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 1
// Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0
// Hardware configuration
`define UART_PRESCALE 1

3
wally-pipelined/config/rv64imc/wally-config.vh
View File

@ -87,9 +87,6 @@
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 0
// Busybear special CSR config to match OVPSim
`define OVPSIM_CSR_CONFIG 0
// Hardware configuration
`define UART_PRESCALE 1

2
wally-pipelined/src/privileged/csrm.sv
View File

@ -162,7 +162,7 @@ module csrm #(parameter
flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
generate
if (`OVPSIM_CSR_CONFIG)
if (`BUSYBEAR == 1)
flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW);
else if (`BUILDROOT == 1)
flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], 32'h0, MCOUNTEREN_REGW);

2
wally-pipelined/src/privileged/csrs.sv
View File

@ -89,7 +89,7 @@ module csrs #(parameter
flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, `XLEN'b0, SCAUSE_REGW);
flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
if (`OVPSIM_CSR_CONFIG)
if (`BUSYBEAR == 1)
flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW);
else if (`BUILDROOT == 1)
flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], 32'h0, SCOUNTEREN_REGW);