forked from Github_Repos/cvw
Partially working icache.
The current issue is a StallF is required to halt the icache from getting an updated PCF. However if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and the icache FSM is never allowed to complete.
This commit is contained in:
Ross Thompson
parent
7b3735fc25
commit
d8ab7a5de2
@ -9,26 +9,26 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/functionRadix/fun
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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@ -172,6 +172,8 @@ add wave -noupdate -expand -group icache -expand -group {fsm out and control} /t
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBByteLength
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBOFFETWIDTH
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/BlockByteLength
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@ -179,34 +181,35 @@ add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/i
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWritePAdr
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadTag
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadAddr
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadPAdr
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WritePAdr
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteSet
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteTag
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWritePAdr
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadTag
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadAddr
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadPAdr
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WritePAdr
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteSet
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteTag
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add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPFinalF
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add wave -noupdate -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCNextPF
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add wave -noupdate -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPFinalF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/ICacheMemReadData
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/ReadLine
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@ -214,9 +217,11 @@ add wave -noupdate -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/ic
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add wave -noupdate -label {read offset} -radix unsigned -childformat {{(4) -radix unsigned} {(3) -radix unsigned} {(2) -radix unsigned} {(1) -radix unsigned} {(0) -radix unsigned}} -subitemconfig {{/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[4]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[3]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[2]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[1]} {-radix unsigned} {/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[0]} {-radix unsigned}} /testbench/dut/hart/ifu/icache/cachemem/offset
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
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add wave -noupdate /testbench/dut/hart/ifu/CompressedF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/SpillDataBlock0
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF_q
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {44 ns} 0} {{Cursor 2} {9098514 ns} 0}
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quietly wave cursor active 2
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WaveRestoreCursors {{Cursor 2} {9808584 ns} 0} {{Cursor 3} {9808065 ns} 0} {{Cursor 4} {535 ns} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 513
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configure wave -justifyvalue left
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@ -231,4 +236,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {9098483 ns} {9098569 ns}
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WaveRestoreZoom {9808255 ns} {9808913 ns}
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@ -140,19 +140,41 @@ module icachecontroller #(parameter LINESIZE = 256) (
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localparam STATE_HIT_SPILL_MISS_FETCH_DONE = 3; // write data into SRAM/LUT
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localparam STATE_HIT_SPILL_MERGE = 4; // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL.
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localparam STATE_MISS_FETCH_WDV = 5; // aligned miss, issue read to AHB and wait for data.
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localparam STATE_MISS_FETCH_DONE = 6; // write data into SRAM/LUT
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localparam STATE_MISS_READ = 7; // read block 1 from SRAM/LUT
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// a challenge is the spill signal gets us out of the ready state and moves us to
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// 1 of the 2 spill branches. However the original fsm design had us return to
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// the ready state when the spill + hits/misses were fully resolved. The problem
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// is the spill signal is based on PCPF so when we return to READY to check if the
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// cache has a hit it still expresses spill. We can fix in 1 of two ways.
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// 1. we can add 1 extra state at the end of each spill branch to returns the instruction
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// to the CPU advancing the CPU and icache to the next instruction.
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// 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get
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// to the READY state.
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// The first first option is more robust and increases the number of states by 2. The
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// second option is seams like it should work, but I worry there is a hidden interaction
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// between CPU stalling and that register.
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// Picking option 1.
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localparam STATE_MISS_SPILL_FETCH_WDV = 8; // spill, miss on block 0, issue read to AHB and wait
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localparam STATE_MISS_SPILL_FETCH_DONE = 9; // write data into SRAM/LUT
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localparam STATE_MISS_SPILL_READ1 = 10; // read block 0 from SRAM/LUT
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localparam STATE_MISS_SPILL_2 = 11; // return to ready if hit or do second block update.
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localparam STATE_MISS_SPILL_MISS_FETCH_WDV = 12; // miss on block 1, issue read to AHB and wait
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localparam STATE_MISS_SPILL_MISS_FETCH_DONE = 13; // write data to SRAM/LUT
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localparam STATE_MISS_SPILL_MERGE = 14; // read block 0 of CPU access,
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localparam STATE_HIT_SPILL_FINAL = 5; // this state replicates STATE_READY's replay of the
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// spill access but does nto consider spill. It also does not do another operation.
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localparam STATE_INVALIDATE = 15; // *** not sure if invalidate or evict? invalidate by cache block or address?
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localparam STATE_MISS_FETCH_WDV = 6; // aligned miss, issue read to AHB and wait for data.
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localparam STATE_MISS_FETCH_DONE = 7; // write data into SRAM/LUT
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localparam STATE_MISS_READ = 8; // read block 1 from SRAM/LUT
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localparam STATE_MISS_SPILL_FETCH_WDV = 9; // spill, miss on block 0, issue read to AHB and wait
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localparam STATE_MISS_SPILL_FETCH_DONE = 10; // write data into SRAM/LUT
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localparam STATE_MISS_SPILL_READ1 = 11; // read block 0 from SRAM/LUT
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localparam STATE_MISS_SPILL_2 = 12; // return to ready if hit or do second block update.
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localparam STATE_MISS_SPILL_MISS_FETCH_WDV = 13; // miss on block 1, issue read to AHB and wait
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localparam STATE_MISS_SPILL_MISS_FETCH_DONE = 14; // write data to SRAM/LUT
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localparam STATE_MISS_SPILL_MERGE = 15; // read block 0 of CPU access,
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localparam STATE_MISS_SPILL_FINAL = 16; // this state replicates STATE_READY's replay of the
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// spill access but does nto consider spill. It also does not do another operation.
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localparam STATE_INVALIDATE = 17; // *** not sure if invalidate or evict? invalidate by cache block or address?
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localparam AHBByteLength = `XLEN / 8;
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localparam AHBOFFETWIDTH = $clog2(AHBByteLength);
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@ -164,7 +186,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
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localparam WORDSPERLINE = LINESIZE/`XLEN;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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logic [3:0] CurrState, NextState;
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logic [4:0] CurrState, NextState;
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logic hit, spill;
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logic SavePC;
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logic [1:0] PCMux;
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@ -213,7 +235,8 @@ module icachecontroller #(parameter LINESIZE = 256) (
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assign PCSpillF = PCPF + 2'b10;
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// now we have to select between these three PCs
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assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextPF; // *** don't like the stallf
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assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextPF; // *** don't like the stallf
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//assign PCPreFinalF = PCMux[0] ? PCPF : PCNextPF; // *** don't like the stallf
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assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF;
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@ -347,12 +370,12 @@ module icachecontroller #(parameter LINESIZE = 256) (
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-----/\----- EXCLUDED -----/\----- */
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// the FSM is always runing, do not stall.
|
||||
flopr #(4) stateReg(.clk(clk),
|
||||
flopr #(5) stateReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.d(NextState),
|
||||
.q(CurrState));
|
||||
|
||||
assign spill = PCPF[5:1] == 5'b1_1111 ? 1'b1 : 1'b0;
|
||||
assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
|
||||
assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit.
|
||||
assign FetchCountFlag = FetchCount == FetchCountThreshold;
|
||||
|
||||
@ -366,6 +389,8 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
spillSave = 1'b0;
|
||||
PCMux = 2'b00;
|
||||
ICacheReadEn = 1'b0;
|
||||
SavePC = 1'b0;
|
||||
ICacheStallF = 1'b1;
|
||||
|
||||
case (CurrState)
|
||||
|
||||
@ -373,15 +398,19 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
PCMux = 2'b00;
|
||||
ICacheReadEn = 1'b1;
|
||||
if (hit & ~spill) begin
|
||||
SavePC = 1'b1;
|
||||
ICacheStallF = 1'b0;
|
||||
NextState = STATE_READY;
|
||||
end else if (hit & spill) begin
|
||||
spillSave = 1'b1;
|
||||
PCMux = 2'b10;
|
||||
NextState = STATE_HIT_SPILL;
|
||||
end else if (~hit & ~spill) begin
|
||||
CntReset = 1'b1;
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
end else if (~hit & spill) begin
|
||||
CntReset = 1'b1;
|
||||
PCMux = 2'b10;
|
||||
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
@ -394,7 +423,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
UnalignedSelect = 1'b1;
|
||||
ICacheReadEn = 1'b1;
|
||||
if (hit) begin
|
||||
NextState = STATE_READY;
|
||||
NextState = STATE_HIT_SPILL_FINAL;
|
||||
end else
|
||||
CntReset = 1'b1;
|
||||
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
|
||||
@ -418,7 +447,15 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
PCMux = 2'b10;
|
||||
UnalignedSelect = 1'b1;
|
||||
ICacheReadEn = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
NextState = STATE_HIT_SPILL_FINAL;
|
||||
end
|
||||
STATE_HIT_SPILL_FINAL: begin
|
||||
ICacheReadEn = 1'b1;
|
||||
PCMux = 2'b00;
|
||||
UnalignedSelect = 1'b1;
|
||||
SavePC = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
ICacheStallF = 1'b0;
|
||||
end
|
||||
|
||||
// branch 3 miss no spill
|
||||
@ -472,7 +509,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
CntReset = 1'b1;
|
||||
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
NextState = STATE_MISS_SPILL_FINAL;
|
||||
end
|
||||
end
|
||||
STATE_MISS_SPILL_MISS_FETCH_WDV: begin
|
||||
@ -494,7 +531,15 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
PCMux = 2'b10;
|
||||
UnalignedSelect = 1'b1;
|
||||
ICacheReadEn = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
NextState = STATE_MISS_SPILL_FINAL;
|
||||
end
|
||||
STATE_MISS_SPILL_FINAL: begin
|
||||
ICacheReadEn = 1'b1;
|
||||
PCMux = 2'b00;
|
||||
UnalignedSelect = 1'b1;
|
||||
SavePC = 1'b1;
|
||||
ICacheStallF = 1'b0;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
default: begin
|
||||
PCMux = 2'b01;
|
||||
@ -508,9 +553,10 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
// stall CPU any time we are not in the ready state. any other state means the
|
||||
// cache is either requesting data from the memory interface or handling a
|
||||
// spill over two cycles.
|
||||
assign ICacheStallF = ((CurrState != STATE_READY) | ~hit) | reset_q ? 1'b1 : 1'b0;
|
||||
// *** BUG this logic will need to change
|
||||
//assign ICacheStallF = ((CurrState != STATE_READY) | ~hit | spill) | reset_q ? 1'b1 : 1'b0;
|
||||
// save the PC anytime we are in the ready state. The saved value will be used as the PC may not be stable.
|
||||
assign SavePC = (CurrState == STATE_READY) & hit ? 1'b1 : 1'b0;
|
||||
//assign SavePC = ((CurrState == STATE_READY) & hit) & ~spill ? 1'b1 : 1'b0;
|
||||
assign CntEn = PreCntEn & InstrAckF;
|
||||
|
||||
assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
|
||||
@ -571,7 +617,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
.en(~StallF),
|
||||
.d(PCPreFinalF[1]),
|
||||
.q(PCPreFinalF_q[1]));
|
||||
assign FinalInstrRawF = PCPreFinalF_q[1] ? {ICacheMemReadData[31:16], SpillDataBlock0} : ICacheMemReadData;
|
||||
assign FinalInstrRawF = spill ? {ICacheMemReadData[15:0], SpillDataBlock0} : ICacheMemReadData;
|
||||
|
||||
// There is a frustrating issue on the first access.
|
||||
// The cache will not contain any valid data but will contain x's on
|
||||
|
||||
@ -89,7 +89,7 @@ module ifu (
|
||||
|
||||
// branch predictor signals
|
||||
logic SelBPPredF;
|
||||
logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F, PCNext2F;
|
||||
logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
|
||||
logic [3:0] InstrClassD, InstrClassE;
|
||||
|
||||
|
||||
@ -124,11 +124,20 @@ module ifu (
|
||||
.s(PrivilegedChangePCM),
|
||||
.y(PCNext2F));
|
||||
|
||||
// *** try to remove this in the future as it can add a long path.
|
||||
// StallF may arrive late.
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
|
||||
.d1(PCF),
|
||||
.s(StallF),
|
||||
.y(PCNext3F));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
mux2 #(`XLEN) pcmux4(.d0(PCNext2F),
|
||||
.d1(`RESET_VECTOR),
|
||||
.s(reset_q),
|
||||
.y(UnalignedPCNextF));
|
||||
|
||||
.y(UnalignedPCNextF));
|
||||
|
||||
flop #(1) resetReg (.clk(clk),
|
||||
.d(reset),
|
||||
.q(reset_q));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user