forked from Github_Repos/cvw
Put repository of fpdivsqrt with RTL-based adder instead of structural implementation
This commit is contained in:
James E. Stine
parent
49b5fa3994
commit
11c88c15d5
9
wally-pipelined/src/fpu/fpdivsqrt/adder_ip.sv
Executable file
9
wally-pipelined/src/fpu/fpdivsqrt/adder_ip.sv
Executable file
@ -0,0 +1,9 @@
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module adder_ip #(parameter WIDTH=8)
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(input logic [WIDTH-1:0] a, b,
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input logic cin,
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output logic [WIDTH-1:0] y,
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output logic cout);
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assign {cout, y} = a + b + cin;
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endmodule // adder
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51
wally-pipelined/src/fpu/fpdivsqrt/convert_inputs.sv
Executable file
51
wally-pipelined/src/fpu/fpdivsqrt/convert_inputs.sv
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@ -0,0 +1,51 @@
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// This module takes as inputs two operands (op1 and op2)
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// and the result precision (P). Based on the operation and precision,
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// it conditionally converts single precision values to double
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// precision values and modifies the sign of op1.
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// The converted operands are Float1 and Float2.
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module convert_inputs(Float1, Float2b, op1, op2, op_type, P);
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input logic [63:0] op1; // 1st input operand (A)
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input logic [63:0] op2; // 2nd input operand (B)
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input logic P; // Result Precision (0 for double, 1 for single)
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input logic op_type; // Operation
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output logic [63:0] Float1; // Converted 1st input operand
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output logic [63:0] Float2b; // Converted 2nd input operand
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logic [63:0] Float2;
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logic Zexp1; // One if the exponent of op1 is zero
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logic Zexp2; // One if the exponent of op2 is zero
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logic Oexp1; // One if the exponent of op1 is all ones
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logic Oexp2; // One if the exponent of op2 is all ones
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// Test if the input exponent is zero, because if it is then the
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// exponent of the converted number should be zero.
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assign Zexp1 = ~(op1[62] | op1[61] | op1[60] | op1[59] |
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op1[58] | op1[57] | op1[56] | op1[55]);
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assign Zexp2 = ~(op2[62] | op2[61] | op2[60] | op2[59] |
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op2[58] | op2[57] | op2[56] | op2[55]);
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assign Oexp1 = (op1[62] & op1[61] & op1[60] & op1[59] &
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op1[58] & op1[57] & op1[56] & op1[55]);
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assign Oexp2 = (op2[62] & op2[61] & op2[60] & op2[59] &
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op2[58] & op2[57] & op2[56] &op2[55]);
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// Conditionally convert op1. Lower 29 bits are zero for single precision.
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assign Float1[62:29] = P ? {op1[62], {3{(~op1[62]&~Zexp1)|Oexp1}}, op1[61:32]}
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: op1[62:29];
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assign Float1[28:0] = op1[28:0] & {29{~P}};
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// Conditionally convert op2. Lower 29 bits are zero for single precision.
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assign Float2[62:29] = P ? {op2[62], {3{(~op2[62]&~Zexp2)|Oexp2}}, op2[61:32]}
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: op2[62:29];
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assign Float2[28:0] = op2[28:0] & {29{~P}};
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// Set the sign of Float1 based on its original sign
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assign Float1[63] = op1[63];
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assign Float2[63] = op2[63];
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// For sqrt, assign Float2 same as Float1 for simplicity
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assign Float2b = op_type ? Float1 : Float2;
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endmodule // convert_inputs
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301
wally-pipelined/src/fpu/fpdivsqrt/divconvDP.sv
Executable file
301
wally-pipelined/src/fpu/fpdivsqrt/divconvDP.sv
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@ -0,0 +1,301 @@
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`timescale 1ps/1ps
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module divconv (q1, qm1, qp1, q0, qm0, qp0,
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rega_out, regb_out, regc_out, regd_out,
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regr_out, d, n,
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sel_muxa, sel_muxb, sel_muxr,
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reset, clk,
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load_rega, load_regb, load_regc, load_regd,
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load_regr, load_regs, load_regp,
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P, op_type, exp_odd);
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input logic [52:0] d, n;
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input logic [2:0] sel_muxa, sel_muxb;
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input logic sel_muxr;
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input logic load_rega, load_regb, load_regc, load_regd;
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input logic load_regr, load_regs;
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input logic load_regp;
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input logic P;
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input logic op_type;
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input logic exp_odd;
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input logic reset;
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input logic clk;
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output logic [63:0] q1, qp1, qm1;
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output logic [63:0] q0, qp0, qm0;
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output logic [63:0] rega_out, regb_out, regc_out, regd_out;
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output logic [127:0] regr_out;
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supply1 vdd;
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supply0 vss;
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logic [63:0] muxa_out, muxb_out;
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logic [10:0] ia_div, ia_sqrt;
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logic [63:0] ia_out;
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logic [127:0] mul_out;
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logic [63:0] q_out1, qm_out1, qp_out1;
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logic [63:0] q_out0, qm_out0, qp_out0;
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logic [63:0] mcand, mplier, mcand_q;
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logic [63:0] twocmp_out;
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logic [64:0] three;
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logic [127:0] Carry, Carry2;
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logic [127:0] Sum, Sum2;
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logic [127:0] constant, constant2;
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logic [63:0] q_const, qp_const, qm_const;
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logic [63:0] d2, n2;
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logic [11:0] d3;
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// Check if exponent is odd for sqrt
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// If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA
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assign d2 = (exp_odd&op_type) ? {vss,d,10'h0} : {d,11'h0};
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assign n2 = op_type ? d2 : {n,11'h0};
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// IA div/sqrt
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sbtm ia1 (d[52:41], ia_div);
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sbtm2 ia2 (d2[63:52], ia_sqrt);
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assign ia_out = op_type ? {ia_sqrt, {53{1'b0}}} : {ia_div, {53{1'b0}}};
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// Choose IA or iteration
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mux6 #(64) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out);
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mux5 #(64) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out);
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// Deal with remainder if [0.5, 1) instead of [1, 2)
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mux2 #(128) mx3a ({~n, {75{1'b1}}}, {{1'b1}, ~n, {74{1'b1}}}, q1[63], constant2);
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// Select Mcand, Remainder/Q''
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mux2 #(128) mx3 (128'h0, constant2, sel_muxr, constant);
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// Select mcand - remainder should always choose q1 [1,2) because
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// adjustment of N in the from XX.FFFFFFF
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mux2 #(64) mx4 (q0, q1, q1[63], mcand_q);
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mux2 #(64) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier);
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mux2 #(64) mx6 (muxa_out, mcand_q, sel_muxr, mcand);
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// TDM multiplier (carry/save)
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multiplier mult1 (mcand, mplier, Sum, Carry);
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// Q*D - N (reversed but changed in rounder.v to account for sign reversal)
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csa #(128) csa1 (Sum, Carry, constant, Sum2, Carry2);
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// Add ulp for subtraction in remainder
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mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out);
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// Constant for Q''
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mux2 #(64) mx8 ({64'h0000_0000_0000_0200}, {64'h0000_0040_0000_0000}, P, q_const);
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mux2 #(64) mx9 ({64'h0000_0000_0000_0A00}, {64'h0000_0140_0000_0000}, P, qp_const);
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mux2 #(64) mxA ({64'hFFFF_FFFF_FFFF_F9FF}, {64'hFFFF_FF3F_FFFF_FFFF}, P, qm_const);
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logic [127:0] Sum_pipe;
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logic [127:0] Carry_pipe;
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logic muxr_pipe;
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logic rega_pipe;
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logic regb_pipe;
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logic regc_pipe;
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logic regd_pipe;
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logic regs_pipe;
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logic regr_pipe;
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logic P_pipe;
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logic op_type_pipe;
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logic [63:0] q_const_pipe;
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logic [63:0] qm_const_pipe;
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logic [63:0] qp_const_pipe;
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// Pipeline Stage 2 of iteration for Goldschmidt's algorithm
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flopenr #(128) regp1 (clk, reset, load_regp, Sum2, Sum_pipe);
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flopenr #(128) regp2 (clk, reset, load_regp, Carry2, Carry_pipe);
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flopenr #(1) regp3 (clk, reset, load_regp, muxr_out, muxr_pipe);
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flopenr #(1) regp4 (clk, reset, load_regp, load_rega, rega_pipe);
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flopenr #(1) regp5 (clk, reset, load_regp, load_regb, regb_pipe);
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flopenr #(1) regp6 (clk, reset, load_regp, load_regc, regc_pipe);
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flopenr #(1) regp7 (clk, reset, load_regp, load_regd, regd_pipe);
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flopenr #(1) regp8 (clk, reset, load_regp, load_regs, regs_pipe);
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flopenr #(1) regp9 (clk, reset, load_regp, load_regr, regr_pipe);
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flopenr #(1) regpA (clk, reset, load_regp, P, P_pipe);
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flopenr #(1) regpB (clk, reset, load_regp, op_type, op_type_pipe);
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flopenr #(64) regpC (clk, reset, load_regp, q_const, q_const_pipe);
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flopenr #(64) regpD (clk, reset, load_regp, qp_const, qp_const_pipe);
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flopenr #(64) regpE (clk, reset, load_regp, qm_const, qm_const_pipe);
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// CPA (from CSA)/Remainder addition/subtraction
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adder_ip #(128) cpa1 (Sum_pipe, Carry_pipe, muxr_pipe, mul_out, cout1);
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// ldf128 cpa1 (cout1, mul_out, Sum_pipe, Carry_pipe, muxr_pipe);
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// One's complement instead of two's complement (for hw efficiency)
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assign three = {~mul_out[126] , mul_out[126], ~mul_out[125:63]};
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mux2 #(64) mxTC (~mul_out[126:63], three[64:1], op_type_pipe, twocmp_out);
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// Assuming [1,2) - q1
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adder_ip #(64) cpa2 (regb_out, q_const_pipe, 1'b0, q_out1, cout2);
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adder_ip #(64) cpa3 (regb_out, qp_const_pipe, 1'b0, qp_out1, cout3);
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adder_ip #(64) cpa4 (regb_out, qm_const_pipe, 1'b1, qm_out1, cout4);
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adder_ip #(64) cpa5 ({regb_out[62:0], vss}, q_const_pipe, 1'b0, q_out0, cout5);
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adder_ip #(64) cpa6 ({regb_out[62:0], vss}, qp_const_pipe, 1'b0, qp_out0, cout6);
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adder_ip #(64) cpa7 ({regb_out[62:0], vss}, qm_const_pipe, 1'b1, qm_out0, cout7);
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//ldf64 cpa2 (cout2, q_out1, regb_out, q_const_pipe, 1'b0);
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//ldf64 cpa3 (cout3, qp_out1, regb_out, qp_const_pipe, 1'b0);
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//ldf64 cpa4 (cout4, qm_out1, regb_out, qm_const_pipe, 1'b1);
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// Assuming [0.5,1) - q0
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//ldf64 cpa5 (cout5, q_out0, {regb_out[62:0], vss}, q_const_pipe, 1'b0);
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//ldf64 cpa6 (cout6, qp_out0, {regb_out[62:0], vss}, qp_const_pipe, 1'b0);
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//ldf64 cpa7 (cout7, qm_out0, {regb_out[62:0], vss}, qm_const_pipe, 1'b1);
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// regs
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flopenr #(64) regc (clk, reset, regc_pipe, twocmp_out, regc_out);
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flopenr #(64) regb (clk, reset, regb_pipe, mul_out[126:63], regb_out);
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flopenr #(64) rega (clk, reset, rega_pipe, mul_out[126:63], rega_out);
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flopenr #(64) regd (clk, reset, regd_pipe, mul_out[126:63], regd_out);
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// remainder
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flopenr #(128) regr (clk, reset, regr_pipe, mul_out, regr_out);
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// Assuming [1,2)
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flopenr #(64) rege (clk, reset, regs_pipe, {q_out1[63:39], (q_out1[38:10] & {29{~P_pipe}}), 10'h0}, q1);
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flopenr #(64) regf (clk, reset, regs_pipe, {qm_out1[63:39], (qm_out1[38:10] & {29{~P_pipe}}), 10'h0}, qm1);
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flopenr #(64) regg (clk, reset, regs_pipe, {qp_out1[63:39], (qp_out1[38:10] & {29{~P_pipe}}), 10'h0}, qp1);
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// Assuming [0,1)
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flopenr #(64) regh (clk, reset, regs_pipe, {q_out0[63:39], (q_out0[38:10] & {29{~P_pipe}}), 10'h0}, q0);
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flopenr #(64) regj (clk, reset, regs_pipe, {qm_out0[63:39], (qm_out0[38:10] & {29{~P_pipe}}), 10'h0}, qm0);
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flopenr #(64) regk (clk, reset, regs_pipe, {qp_out0[63:39], (qp_out0[38:10] & {29{~P_pipe}}), 10'h0}, qp0);
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endmodule // divconv
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module adder #(parameter WIDTH=8)
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(input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y);
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assign y = a + b;
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endmodule // adder
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module flopenr #(parameter WIDTH = 8)
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(input logic clk, reset, en,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= #10 0;
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else if (en) q <= #10 d;
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endmodule // flopenr
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module flopr #(parameter WIDTH = 8)
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(input logic clk, reset,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= #10 0;
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else q <= #10 d;
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endmodule // flopr
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module flopenrc #(parameter WIDTH = 8)
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(input logic clk, reset, en, clear,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= #10 0;
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else if (en)
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if (clear) q <= #10 0;
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else q <= #10 d;
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endmodule // flopenrc
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module floprc #(parameter WIDTH = 8)
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(input logic clk, reset, clear,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= #10 0;
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else
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if (clear) q <= #10 0;
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else q <= #10 d;
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endmodule // floprc
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module mux2 #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y);
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assign y = s ? d1 : d0;
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endmodule // mux2
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module mux3 #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] d0, d1, d2,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? d2 : (s[0] ? d1 : d0);
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endmodule // mux3
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module mux4 #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] d0, d1, d2, d3,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
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endmodule // mux4
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module mux5 #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] d0, d1, d2, d3, d4,
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input logic [2:0] s,
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output logic [WIDTH-1:0] y);
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always_comb
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casez (s)
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3'b000 : y = d0;
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3'b001 : y = d1;
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3'b010 : y = d2;
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3'b011 : y = d3;
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3'b1?? : y = d4;
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endcase // casez (s)
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endmodule // mux5
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module mux6 #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5,
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input logic [2:0] s,
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output logic [WIDTH-1:0] y);
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always_comb
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casez (s)
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3'b000 : y = d0;
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3'b001 : y = d1;
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3'b010 : y = d2;
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3'b011 : y = d3;
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3'b10? : y = d4;
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3'b11? : y = d5;
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endcase // casez (s)
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endmodule // mux6
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module eqcmp #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] a, b,
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output logic y);
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assign y = (a == b);
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endmodule // eqcmp
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module fa (input logic a, b, c, output logic sum, carry);
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assign sum = a^b^c;
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assign carry = a&b|a&c|b&c;
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endmodule // fa
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module csa #(parameter WIDTH=8)
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(input logic [WIDTH-1:0] a, b, c,
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output logic [WIDTH-1:0] sum, carry);
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logic [WIDTH:0] carry_temp;
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genvar i;
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generate
|
||||
for (i=0;i<WIDTH;i=i+1)
|
||||
begin : genbit
|
||||
fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
|
||||
end
|
||||
endgenerate
|
||||
assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0};
|
||||
|
||||
endmodule // csa
|
||||
96
wally-pipelined/src/fpu/fpdivsqrt/exception.sv
Executable file
96
wally-pipelined/src/fpu/fpdivsqrt/exception.sv
Executable file
@ -0,0 +1,96 @@
|
||||
// Exception logic for the floating point adder. Note: We may
|
||||
// actually want to move to where the result is computed.
|
||||
|
||||
module exception (Ztype, Invalid, Denorm, ANorm, BNorm, A, B, op_type);
|
||||
|
||||
input logic [63:0] A; // 1st input operand (op1)
|
||||
input logic [63:0] B; // 2nd input operand (op2)
|
||||
input logic op_type; // Determine operation
|
||||
|
||||
output logic [2:0] Ztype; // Indicates type of result (Z)
|
||||
output logic Invalid; // Invalid operation exception
|
||||
output logic Denorm; // Denormalized input
|
||||
output logic ANorm; // A is not zero or Denorm
|
||||
output logic BNorm; // B is not zero or Denorm
|
||||
|
||||
logic AzeroM; // '1' if the mantissa of A is zero
|
||||
logic BzeroM; // '1' if the mantissa of B is zero
|
||||
logic AzeroE; // '1' if the exponent of A is zero
|
||||
logic BzeroE; // '1' if the exponent of B is zero
|
||||
logic AonesE; // '1' if the exponent of A is all ones
|
||||
logic BonesE; // '1' if the exponent of B is all ones
|
||||
logic ADenorm; // '1' if A is a denomalized number
|
||||
logic BDenorm; // '1' if B is a denomalized number
|
||||
logic AInf; // '1' if A is infinite
|
||||
logic BInf; // '1' if B is infinite
|
||||
logic AZero; // '1' if A is 0
|
||||
logic BZero; // '1' if B is 0
|
||||
logic ANaN; // '1' if A is a not-a-number
|
||||
logic BNaN; // '1' if B is a not-a-number
|
||||
logic ASNaN; // '1' if A is a signalling not-a-number
|
||||
logic BSNaN; // '1' if B is a signalling not-a-number
|
||||
logic ZQNaN; // '1' if result Z is a quiet NaN
|
||||
logic ZInf; // '1' if result Z is an infnity
|
||||
logic square_root; // '1' if square root operation
|
||||
logic Zero; // '1' if result is zero
|
||||
|
||||
parameter [51:0] fifty_two_zeros = 52'h0; // Use parameter?
|
||||
|
||||
// Determine if mantissas are all zeros
|
||||
assign AzeroM = (A[51:0] == fifty_two_zeros);
|
||||
assign BzeroM = (B[51:0] == fifty_two_zeros);
|
||||
|
||||
// Determine if exponents are all ones or all zeros
|
||||
assign AonesE = A[62]&A[61]&A[60]&A[59]&A[58]&A[57]&A[56]&A[55]&A[54]&A[53]&A[52];
|
||||
assign BonesE = B[62]&B[61]&B[60]&B[59]&B[58]&B[57]&B[56]&B[55]&B[54]&B[53]&B[52];
|
||||
assign AzeroE = ~(A[62]|A[61]|A[60]|A[59]|A[58]|A[57]|A[56]|A[55]|A[54]|A[53]|A[52]);
|
||||
assign BzeroE = ~(B[62]|B[61]|B[60]|B[59]|B[58]|B[57]|B[56]|B[55]|B[54]|B[53]|B[52]);
|
||||
|
||||
// Determine special cases. Note: Zero is not really a special case.
|
||||
assign ADenorm = AzeroE & ~AzeroM;
|
||||
assign BDenorm = BzeroE & ~BzeroM;
|
||||
assign AInf = AonesE & AzeroM;
|
||||
assign BInf = BonesE & BzeroM;
|
||||
assign ANaN = AonesE & ~AzeroM;
|
||||
assign BNaN = BonesE & ~BzeroM;
|
||||
assign ASNaN = ANaN & A[50];
|
||||
assign BSNaN = ANaN & A[50];
|
||||
assign AZero = AzeroE & AzeroM;
|
||||
assign BZero = BzeroE & BzeroE;
|
||||
|
||||
// A and B are normalized if their exponents are not zero.
|
||||
assign ANorm = ~AzeroE;
|
||||
assign BNorm = ~BzeroE;
|
||||
|
||||
// An "Invalid Operation" exception occurs if (A or B is a signalling NaN)
|
||||
// or (A and B are both Infinite)
|
||||
assign Invalid = ASNaN | BSNaN | (((AInf & BInf) | (AZero & BZero))&~op_type) |
|
||||
(A[63] & op_type);
|
||||
|
||||
// The Denorm flag is set if A is denormlized or if B is normalized
|
||||
assign Denorm = ADenorm | BDenorm;
|
||||
|
||||
// The result is a quiet NaN if (an "Invalid Operation" exception occurs)
|
||||
// or (A is a NaN) or (B is a NaN).
|
||||
assign ZQNaN = Invalid | ANaN | BNaN;
|
||||
|
||||
// The result is zero
|
||||
assign Zero = (AZero | BInf)&~op_type | AZero&op_type;
|
||||
|
||||
// The result is +Inf if ((A is Inf) or (B is 0)) and (the
|
||||
// result is not a quiet NaN).
|
||||
assign ZInf = (AInf | BZero)&~ZQNaN&~op_type | AInf&op_type&~ZQNaN;
|
||||
|
||||
// Set the type of the result as follows:
|
||||
// Ztype Result
|
||||
// 000 Normal
|
||||
// 001 Quiet NaN
|
||||
// 010 Infinity
|
||||
// 011 Zero
|
||||
// 110 DivZero
|
||||
assign Ztype[0] = ZQNaN | Zero;
|
||||
assign Ztype[1] = ZInf | Zero;
|
||||
assign Ztype[2] = BZero&~op_type;
|
||||
|
||||
endmodule // exception
|
||||
|
||||
56
wally-pipelined/src/fpu/fpdivsqrt/f32_div_rd.do
Executable file
56
wally-pipelined/src/fpu/fpdivsqrt/f32_div_rd.do
Executable file
@ -0,0 +1,56 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f32_div_rd.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9269690000 ns
|
||||
quit
|
||||
56
wally-pipelined/src/fpu/fpdivsqrt/f32_div_rne.do
Executable file
56
wally-pipelined/src/fpu/fpdivsqrt/f32_div_rne.do
Executable file
@ -0,0 +1,56 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f32_div_rne.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9269690000 ns
|
||||
quit
|
||||
56
wally-pipelined/src/fpu/fpdivsqrt/f32_div_ru.do
Executable file
56
wally-pipelined/src/fpu/fpdivsqrt/f32_div_ru.do
Executable file
@ -0,0 +1,56 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f32_div_ru.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9269690000 ns
|
||||
quit
|
||||
56
wally-pipelined/src/fpu/fpdivsqrt/f32_div_rz.do
Executable file
56
wally-pipelined/src/fpu/fpdivsqrt/f32_div_rz.do
Executable file
@ -0,0 +1,56 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f32_div_rz.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9269690000 ns
|
||||
quit
|
||||
55
wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rd.do
Executable file
55
wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rd.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f32_sqrt_rd.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9234244000 ns
|
||||
quit
|
||||
55
wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rne.do
Executable file
55
wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rne.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f32_sqrt_rne.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9234244000 ns
|
||||
quit
|
||||
55
wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_ru.do
Executable file
55
wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_ru.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f32_sqrt_ru.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9234244000 ns
|
||||
quit
|
||||
55
wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rz.do
Executable file
55
wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rz.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f32_sqrt_rz.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9234244000 ns
|
||||
quit
|
||||
56
wally-pipelined/src/fpu/fpdivsqrt/f64_div_rd.do
Executable file
56
wally-pipelined/src/fpu/fpdivsqrt/f64_div_rd.do
Executable file
@ -0,0 +1,56 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f64_div_rd.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 350
|
||||
configure wave -valuecolwidth 200
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9338600000 ns
|
||||
quit
|
||||
57
wally-pipelined/src/fpu/fpdivsqrt/f64_div_rne.do
Executable file
57
wally-pipelined/src/fpu/fpdivsqrt/f64_div_rne.do
Executable file
@ -0,0 +1,57 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f64_div_rne.sv
|
||||
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9398600000 ns
|
||||
quit
|
||||
56
wally-pipelined/src/fpu/fpdivsqrt/f64_div_ru.do
Executable file
56
wally-pipelined/src/fpu/fpdivsqrt/f64_div_ru.do
Executable file
@ -0,0 +1,56 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f64_div_ru.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9338600000 ns
|
||||
quit
|
||||
56
wally-pipelined/src/fpu/fpdivsqrt/f64_div_rz.do
Executable file
56
wally-pipelined/src/fpu/fpdivsqrt/f64_div_rz.do
Executable file
@ -0,0 +1,56 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f64_div_rz.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 350
|
||||
configure wave -valuecolwidth 250
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 9398600000 ns
|
||||
quit
|
||||
55
wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rd.do
Executable file
55
wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rd.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f64_sqrt_rd.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 94364000 ns
|
||||
quit
|
||||
55
wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rne.do
Executable file
55
wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rne.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f64_sqrt_rne.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 94364000 ns
|
||||
quit
|
||||
55
wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_ru.do
Executable file
55
wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_ru.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f64_sqrt_ru.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 94364000 ns
|
||||
quit
|
||||
55
wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rz.do
Executable file
55
wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rz.do
Executable file
@ -0,0 +1,55 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv tb_f64_sqrt_rz.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
#view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
-- 39,052 vectors, 390,565ns
|
||||
run 94364000 ns
|
||||
quit
|
||||
109
wally-pipelined/src/fpu/fpdivsqrt/fpdiv.do
Executable file
109
wally-pipelined/src/fpu/fpdivsqrt/fpdiv.do
Executable file
@ -0,0 +1,109 @@
|
||||
# Copyright 1991-2016 Mentor Graphics Corporation
|
||||
#
|
||||
# Modification by Oklahoma State University
|
||||
# Use with Testbench
|
||||
# James Stine, 2008
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# All Rights Reserved.
|
||||
#
|
||||
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
|
||||
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
|
||||
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
|
||||
# Use this run.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do run.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do run.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
vlog adder_ip.sv bk15.v mult_R4_64_64_cs.v ldf128.v ldf64.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm.v divconvDP.sv convert_inputs.sv exception.sv rounder.sv fpdiv.sv test_fpdiv.sv
|
||||
|
||||
# start and run simulation
|
||||
vsim -voptargs=+acc work.tb
|
||||
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
add wave -hex -color gold /tb/dut/clk
|
||||
add wave -hex -color gold /tb/dut/mantissaA
|
||||
add wave -hex -color gold /tb/dut/mantissaB
|
||||
add wave -hex -color gold /tb/dut/op1
|
||||
add wave -hex -color gold /tb/dut/op2
|
||||
add wave -hex -color gold /tb/dut/AS_Result
|
||||
add wave -hex -color gold /tb/dut/Flags
|
||||
add wave -hex -color gold /tb/dut/Denorm
|
||||
#add wave -noupdate -divider -height 32 "exponent"
|
||||
#add wave -hex /tb/dut/exp1
|
||||
#add wave -hex /tb/dut/exp2
|
||||
#add wave -hex /tb/dut/expF
|
||||
#add wave -hex /tb/dut/bias
|
||||
#add wave -hex /tb/dut/exp_diff
|
||||
#add wave -hex /tb/dut/exp_odd
|
||||
#add wave -hex -r /tb/dut/explogic2/*
|
||||
#add wave -hex -r /tb/dut/explogic1/*
|
||||
add wave -noupdate -divider -height 32 "FSM"
|
||||
add wave -hex /tb/dut/control/CURRENT_STATE
|
||||
add wave -hex /tb/dut/control/NEXT_STATE
|
||||
add wave -hex -color #0080ff /tb/dut/control/start
|
||||
add wave -hex -color #0080ff /tb/dut/control/reset
|
||||
add wave -hex -color #0080ff /tb/dut/control/op_type
|
||||
add wave -hex -color #0080ff /tb/dut/control/load_rega
|
||||
add wave -hex -color #0080ff /tb/dut/control/load_regb
|
||||
add wave -hex -color #0080ff /tb/dut/control/load_regc
|
||||
add wave -hex -color #0080ff /tb/dut/control/load_regr
|
||||
add wave -hex -color #0080ff /tb/dut/control/load_regs
|
||||
add wave -hex -color #0080ff /tb/dut/control/sel_muxa
|
||||
add wave -hex -color #0080ff /tb/dut/control/sel_muxb
|
||||
add wave -hex -color #0080ff /tb/dut/control/sel_muxr
|
||||
add wave -hex -color #0080ff /tb/dut/control/done
|
||||
add wave -noupdate -divider -height 32 "Convert"
|
||||
add wave -hex -r /tb/dut/conv1/*
|
||||
add wave -noupdate -divider -height 32 "Exceptions"
|
||||
add wave -hex -r /tb/dut/exc1/*
|
||||
add wave -noupdate -divider -height 32 "Rounder"
|
||||
add wave -hex -r /tb/dut/round1/*
|
||||
add wave -noupdate -divider -height 32 "Pipe State"
|
||||
add wave -hex -r /tb/dut/goldy/Sum_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/Carry_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/muxr_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/rega_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/regb_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/regc_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/regd_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/regs_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/regr_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/P_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/op_type_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/q_const_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/qm_const_pipe;
|
||||
add wave -hex -r /tb/dut/goldy/qp_const_pipe;
|
||||
add wave -noupdate -divider -height 32 "Goldschmidt"
|
||||
add wave -hex -r /tb/dut/goldy/*
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {75 ns}
|
||||
configure wave -namecolwidth 350
|
||||
configure wave -valuecolwidth 250
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
|
||||
-- Run the Simulation
|
||||
run 20ns
|
||||
quit
|
||||
164
wally-pipelined/src/fpu/fpdivsqrt/fpdiv.sv
Executable file
164
wally-pipelined/src/fpu/fpdivsqrt/fpdiv.sv
Executable file
@ -0,0 +1,164 @@
|
||||
//
|
||||
// File name : fpdivP
|
||||
// Title : Floating-Point Divider/Square-Root
|
||||
// project : FPU
|
||||
// Library : fpdiv
|
||||
// Author(s) : James E. Stine, Jr.
|
||||
// Purpose : definition of main unit to floating-point div/sqrt
|
||||
// notes :
|
||||
//
|
||||
// Copyright Oklahoma State University
|
||||
//
|
||||
// Basic Operations
|
||||
//
|
||||
// Step 1: Load operands, set flags, and convert SP to DP
|
||||
// Step 2: Check for special inputs ( +/- Infinity, NaN)
|
||||
// Step 3: Exponent Logic
|
||||
// Step 4: Divide/Sqrt using Goldschmidt
|
||||
// Step 5: Normalize the result.//
|
||||
// Shift left until normalized. Normalized when the value to the
|
||||
// left of the binrary point is 1.
|
||||
// Step 6: Round the result.//
|
||||
// Step 7: Put quotient/remainder onto output.
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
module fpdiv (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
input logic [63:0] op1; // 1st input operand (A)
|
||||
input logic [63:0] op2; // 2nd input operand (B)
|
||||
input logic [1:0] rm; // Rounding mode - specify values
|
||||
input logic op_type; // Function opcode
|
||||
input logic P; // Result Precision (0 for double, 1 for single)
|
||||
input logic OvEn; // Overflow trap enabled
|
||||
input logic UnEn; // Underflow trap enabled
|
||||
|
||||
input logic start;
|
||||
input logic reset;
|
||||
input logic clk;
|
||||
|
||||
output logic [63:0] AS_Result; // Result of operation
|
||||
output logic [4:0] Flags; // IEEE exception flags
|
||||
output logic Denorm; // Denorm on input or output
|
||||
output logic done;
|
||||
|
||||
supply1 vdd;
|
||||
supply0 vss;
|
||||
|
||||
logic [63:0] Float1;
|
||||
logic [63:0] Float2;
|
||||
logic [63:0] IntValue;
|
||||
|
||||
logic [12:0] exp1, exp2, expF;
|
||||
logic [12:0] exp_diff, bias;
|
||||
logic [13:0] exp_sqrt;
|
||||
logic [12:0] exp_s;
|
||||
logic [12:0] exp_c;
|
||||
|
||||
logic [10:0] exponent, exp_pre;
|
||||
logic [63:0] Result;
|
||||
logic [52:0] mantissaA;
|
||||
logic [52:0] mantissaB;
|
||||
logic [63:0] sum, sum_tc, sum_corr, sum_norm;
|
||||
|
||||
logic [5:0] align_shift;
|
||||
logic [5:0] norm_shift;
|
||||
logic [2:0] sel_inv;
|
||||
logic op1_Norm, op2_Norm;
|
||||
logic opA_Norm, opB_Norm;
|
||||
logic Invalid;
|
||||
logic DenormIn, DenormIO;
|
||||
logic [4:0] FlagsIn;
|
||||
logic exp_gt63;
|
||||
logic Sticky_out;
|
||||
logic signResult, sign_corr;
|
||||
logic corr_sign;
|
||||
logic zeroB;
|
||||
logic convert;
|
||||
logic swap;
|
||||
logic sub;
|
||||
|
||||
logic [63:0] q1, qm1, qp1, q0, qm0, qp0;
|
||||
logic [63:0] rega_out, regb_out, regc_out, regd_out;
|
||||
logic [127:0] regr_out;
|
||||
logic [2:0] sel_muxa, sel_muxb;
|
||||
logic sel_muxr;
|
||||
logic load_rega, load_regb, load_regc, load_regd, load_regr;
|
||||
logic load_regp;
|
||||
|
||||
logic donev, sel_muxrv, sel_muxsv;
|
||||
logic [1:0] sel_muxav, sel_muxbv;
|
||||
logic load_regav, load_regbv, load_regcv;
|
||||
logic load_regrv, load_regsv;
|
||||
|
||||
// Convert the input operands to their appropriate forms based on
|
||||
// the orignal operands, the op_type , and their precision P.
|
||||
// Single precision inputs are converted to double precision
|
||||
// and the sign of the first operand is set appropratiately based on
|
||||
// if the operation is absolute value or negation.
|
||||
convert_inputs conv1 (Float1, Float2, op1, op2, op_type, P);
|
||||
|
||||
// Test for exceptions and return the "Invalid Operation" and
|
||||
// "Denormalized" Input Flags. The "sel_inv" is used in
|
||||
// the third pipeline stage to select the result. Also, op1_Norm
|
||||
// and op2_Norm are one if op1 and op2 are not zero or denormalized.
|
||||
// sub is one if the effective operation is subtaction.
|
||||
exception exc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm,
|
||||
Float1, Float2, op_type);
|
||||
|
||||
// Determine Sign/Mantissa
|
||||
assign signResult = ((Float1[63]^Float2[63])&~op_type) | Float1[63]&op_type;
|
||||
assign mantissaA = {vdd, Float1[51:0]};
|
||||
assign mantissaB = {vdd, Float2[51:0]};
|
||||
// Early-ending detection
|
||||
assign early_detection = |mantissaB[31:0];
|
||||
|
||||
// Perform Exponent Subtraction - expA - expB + Bias
|
||||
assign exp1 = {2'b0, Float1[62:52]};
|
||||
assign exp2 = {2'b0, Float2[62:52]};
|
||||
// bias : DP = 2^{11-1}-1 = 1023
|
||||
assign bias = {3'h0, 10'h3FF};
|
||||
// Divide exponent
|
||||
csa #(13) csa1 (exp1, ~exp2, bias, exp_s, exp_c);
|
||||
//exp_add explogic1 (exp_cout1, {open, exp_diff},
|
||||
// {vss, exp_s}, {vss, exp_c}, 1'b1);
|
||||
adder_ip #(14) explogic1 ({vss, exp_s}, {vss, exp_c}, 1'b1, {open, exp_diff}, exp_cout1);
|
||||
|
||||
// Sqrt exponent (check if exponent is odd)
|
||||
assign exp_odd = Float1[52] ? vss : vdd;
|
||||
//exp_add explogic2 (exp_cout2, exp_sqrt,
|
||||
// {vss, exp1}, {4'h0, 10'h3ff}, exp_odd);
|
||||
adder_ip #(14) explogic2 ({vss, exp1}, {4'h0, 10'h3ff}, exp_odd, exp_sqrt, exp_cout2);
|
||||
|
||||
// Choose correct exponent
|
||||
assign expF = op_type ? exp_sqrt[13:1] : exp_diff;
|
||||
|
||||
// Main Goldschmidt/Division Routine
|
||||
divconv goldy (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out,
|
||||
regr_out, mantissaB, mantissaA,
|
||||
sel_muxa, sel_muxb, sel_muxr, reset, clk,
|
||||
load_rega, load_regb, load_regc, load_regd,
|
||||
load_regr, load_regs, load_regp,
|
||||
P, op_type, exp_odd);
|
||||
|
||||
// FSM : control divider
|
||||
fsm_fpdivsqrt control (done, load_rega, load_regb, load_regc, load_regd,
|
||||
load_regr, load_regs, load_regp,
|
||||
sel_muxa, sel_muxb, sel_muxr,
|
||||
clk, reset, start, error, op_type, P);
|
||||
|
||||
// Round the mantissa to a 52-bit value, with the leading one
|
||||
// removed. The rounding units also handles special cases and
|
||||
// set the exception flags.
|
||||
rounder round1 (Result, DenormIO, FlagsIn,
|
||||
rm, P, OvEn, UnEn, expF,
|
||||
sel_inv, Invalid, DenormIn, signResult,
|
||||
q1, qm1, qp1, q0, qm0, qp0, regr_out);
|
||||
|
||||
// Store the final result and the exception flags in registers.
|
||||
flopenr #(64) rega (clk, reset, done, Result, AS_Result);
|
||||
flopenr #(1) regb (clk, reset, done, DenormIO, Denorm);
|
||||
flopenr #(5) regc (clk, reset, done, FlagsIn, Flags);
|
||||
|
||||
endmodule // fpdivP
|
||||
78
wally-pipelined/src/fpu/fpdivsqrt/fpdiv3.in
Executable file
78
wally-pipelined/src/fpu/fpdivsqrt/fpdiv3.in
Executable file
@ -0,0 +1,78 @@
|
||||
.i 6
|
||||
.o 2
|
||||
.ilb SignR rm[1] rm[0] G zero_rem sign_rem
|
||||
.ob M1 M0
|
||||
|
||||
000000 00
|
||||
000001 00
|
||||
000010 00
|
||||
000011 00
|
||||
000100 10
|
||||
000101 00
|
||||
000110 --
|
||||
000111 --
|
||||
|
||||
001000 00
|
||||
001001 01
|
||||
001010 00
|
||||
001011 00
|
||||
001100 00
|
||||
001101 00
|
||||
001110 --
|
||||
001111 --
|
||||
|
||||
010000 10
|
||||
010001 00
|
||||
010010 00
|
||||
010011 00
|
||||
010100 10
|
||||
010101 10
|
||||
010110 --
|
||||
010111 --
|
||||
|
||||
011000 00
|
||||
011001 01
|
||||
011010 00
|
||||
011011 00
|
||||
011100 00
|
||||
011101 00
|
||||
011110 --
|
||||
011111 --
|
||||
|
||||
100000 00
|
||||
100001 00
|
||||
100010 00
|
||||
100011 00
|
||||
100100 10
|
||||
100101 00
|
||||
100110 --
|
||||
100111 --
|
||||
|
||||
101000 00
|
||||
101001 01
|
||||
101010 00
|
||||
101011 00
|
||||
101100 00
|
||||
101101 00
|
||||
101110 --
|
||||
101111 --
|
||||
|
||||
110000 00
|
||||
110001 01
|
||||
110010 00
|
||||
110011 00
|
||||
110100 00
|
||||
110101 00
|
||||
110110 --
|
||||
110111 --
|
||||
|
||||
111000 10
|
||||
111001 00
|
||||
111010 00
|
||||
111011 00
|
||||
111100 10
|
||||
111101 10
|
||||
111110 --
|
||||
111111 --
|
||||
|
||||
.e
|
||||
98
wally-pipelined/src/fpu/fpdivsqrt/fpdiv4.in
Executable file
98
wally-pipelined/src/fpu/fpdivsqrt/fpdiv4.in
Executable file
@ -0,0 +1,98 @@
|
||||
.i 7
|
||||
.o 2
|
||||
.ilb SignR rm[2] rm[1] rm[0] G zero_rem sign_rem
|
||||
.ob M1 M0
|
||||
|
||||
0000000 00
|
||||
0000001 00
|
||||
0000010 00
|
||||
0000011 00
|
||||
0000100 10
|
||||
0000101 00
|
||||
0000110 --
|
||||
0000111 --
|
||||
|
||||
0001000 00
|
||||
0001001 01
|
||||
0001010 00
|
||||
0001011 00
|
||||
0001100 00
|
||||
0001101 00
|
||||
0001110 --
|
||||
0001111 --
|
||||
|
||||
0010000 10
|
||||
0010001 00
|
||||
0010010 00
|
||||
0010011 00
|
||||
0010100 10
|
||||
0010101 10
|
||||
0010110 --
|
||||
0010111 --
|
||||
|
||||
0011000 00
|
||||
0011001 01
|
||||
0011010 00
|
||||
0011011 00
|
||||
0011100 00
|
||||
0011101 00
|
||||
0011110 --
|
||||
0011111 --
|
||||
|
||||
01--000 10
|
||||
01--001 00
|
||||
01--010 00
|
||||
01--011 00
|
||||
01--100 10
|
||||
01--101 10
|
||||
01--110 --
|
||||
01--111 --
|
||||
|
||||
1000000 00
|
||||
1000001 00
|
||||
1000010 00
|
||||
1000011 00
|
||||
1000100 10
|
||||
1000101 00
|
||||
1000110 --
|
||||
1000111 --
|
||||
|
||||
1001000 00
|
||||
1001001 01
|
||||
1001010 00
|
||||
1001011 00
|
||||
1001100 00
|
||||
1001101 00
|
||||
1001110 --
|
||||
1001111 --
|
||||
|
||||
1010000 00
|
||||
1010001 01
|
||||
1010010 00
|
||||
1010011 00
|
||||
1010100 00
|
||||
1010101 00
|
||||
1010110 --
|
||||
1010111 --
|
||||
|
||||
1011000 10
|
||||
1011001 00
|
||||
1011010 00
|
||||
1011011 00
|
||||
1011100 10
|
||||
1011101 10
|
||||
1011110 --
|
||||
1011111 --
|
||||
|
||||
11--000 10
|
||||
11--001 00
|
||||
11--010 00
|
||||
11--011 00
|
||||
11--100 10
|
||||
11--101 10
|
||||
11--110 --
|
||||
11--111 --
|
||||
|
||||
|
||||
|
||||
.e
|
||||
1083
wally-pipelined/src/fpu/fpdivsqrt/fsm.v
Executable file
1083
wally-pipelined/src/fpu/fpdivsqrt/fsm.v
Executable file
File diff suppressed because it is too large
Load Diff
31
wally-pipelined/src/fpu/fpdivsqrt/list.lst
Executable file
31
wally-pipelined/src/fpu/fpdivsqrt/list.lst
Executable file
File diff suppressed because one or more lines are too long
11996
wally-pipelined/src/fpu/fpdivsqrt/mult_R4_64_64_cs.v
Executable file
11996
wally-pipelined/src/fpu/fpdivsqrt/mult_R4_64_64_cs.v
Executable file
File diff suppressed because it is too large
Load Diff
187
wally-pipelined/src/fpu/fpdivsqrt/rounder.sv
Executable file
187
wally-pipelined/src/fpu/fpdivsqrt/rounder.sv
Executable file
@ -0,0 +1,187 @@
|
||||
//
|
||||
// The rounder takes as inputs a 64-bit value to be rounded, A, the
|
||||
// exponent of the value to be rounded, the sign of the final result, Sign,
|
||||
// the precision of the results, P, and the two-bit rounding mode, rm.
|
||||
// It produces a rounded 52-bit result, Z, the exponent of the rounded
|
||||
// result, Z_exp, and a flag that indicates if the result was rounded,
|
||||
// Inexact. The rounding mode has the following values.
|
||||
// rm Modee
|
||||
// 00 round-to-nearest-even
|
||||
// 01 round-toward-zero
|
||||
// 10 round-toward-plus infinity
|
||||
// 11 round-toward-minus infinity
|
||||
//
|
||||
|
||||
module rounder (Result, DenormIO, Flags, rm, P, OvEn,
|
||||
UnEn, exp_diff, sel_inv, Invalid, DenormIn,
|
||||
SignR, q1, qm1, qp1, q0, qm0, qp0, regr_out);
|
||||
|
||||
input logic [1:0] rm;
|
||||
input logic P;
|
||||
input logic OvEn;
|
||||
input logic UnEn;
|
||||
input logic [12:0] exp_diff;
|
||||
input logic [2:0] sel_inv;
|
||||
input logic Invalid;
|
||||
input logic DenormIn;
|
||||
input logic SignR;
|
||||
|
||||
input logic [63:0] q1;
|
||||
input logic [63:0] qm1;
|
||||
input logic [63:0] qp1;
|
||||
input logic [63:0] q0;
|
||||
input logic [63:0] qm0;
|
||||
input logic [63:0] qp0;
|
||||
input logic [127:0] regr_out;
|
||||
|
||||
output logic [63:0] Result;
|
||||
output logic DenormIO;
|
||||
output logic [4:0] Flags;
|
||||
|
||||
supply1 vdd;
|
||||
supply0 vss;
|
||||
|
||||
logic Rsign;
|
||||
logic [10:0] Rexp;
|
||||
logic [12:0] Texp;
|
||||
logic [51:0] Rmant;
|
||||
logic [63:0] Tmant;
|
||||
logic [51:0] Smant;
|
||||
logic Rzero;
|
||||
logic Gdp, Gsp, G;
|
||||
logic UnFlow_SP, UnFlow_DP, UnderFlow;
|
||||
logic OvFlow_SP, OvFlow_DP, OverFlow;
|
||||
logic Inexact;
|
||||
logic Round_zero;
|
||||
logic Infinite;
|
||||
logic VeryLarge;
|
||||
logic Largest;
|
||||
logic Div0;
|
||||
logic Adj_exp;
|
||||
logic Valid;
|
||||
logic NaN;
|
||||
logic Texp_l7z;
|
||||
logic Texp_l7o;
|
||||
logic OvCon;
|
||||
logic [1:0] mux_mant;
|
||||
logic sign_rem;
|
||||
logic [63:0] q, qm, qp;
|
||||
logic exp_ovf, exp_ovfSP, exp_ovfDP;
|
||||
|
||||
// Remainder = 0?
|
||||
assign zero_rem = ~(|regr_out);
|
||||
// Remainder Sign
|
||||
assign sign_rem = ~regr_out[127];
|
||||
// choose correct Guard bit [1,2) or [0,1)
|
||||
assign Gdp = q1[63] ? q1[10] : q0[10];
|
||||
assign Gsp = q1[63] ? q1[39] : q0[39];
|
||||
assign G = P ? Gsp : Gdp;
|
||||
// Selection of Rounding (from logic/switching)
|
||||
assign mux_mant[1] = (SignR&rm[1]&rm[0]&G) | (!SignR&rm[1]&!rm[0]&G) |
|
||||
(!rm[1]&!rm[0]&G&!sign_rem) |
|
||||
(SignR&rm[1]&rm[0]&!zero_rem&!sign_rem) |
|
||||
(!SignR&rm[1]&!rm[0]&!zero_rem&!sign_rem);
|
||||
assign mux_mant[0] = (!SignR&rm[0]&!G&!zero_rem&sign_rem) |
|
||||
(!rm[1]&rm[0]&!G&!zero_rem&sign_rem) |
|
||||
(SignR&rm[1]&!rm[0]&!G&!zero_rem&sign_rem);
|
||||
|
||||
// Which Q?
|
||||
mux2 #(64) mx1 (q0, q1, q1[63], q);
|
||||
mux2 #(64) mx2 (qm0, qm1, q1[63], qm);
|
||||
mux2 #(64) mx3 (qp0, qp1, q1[63], qp);
|
||||
// Choose Q, Q+1, Q-1
|
||||
mux3 #(64) mx4 (q, qm, qp, mux_mant, Tmant);
|
||||
assign Smant = Tmant[62:11];
|
||||
// Compute the value of the exponent
|
||||
// exponent is modified if we choose:
|
||||
// 1.) we choose any qm0, qp0, q0 (since we shift mant)
|
||||
// 2.) we choose qp and we overflow (for RU)
|
||||
assign exp_ovf = |{qp[62:40], (qp[39:11] & {29{~P}})};
|
||||
assign Texp = exp_diff - {{13{vss}}, ~q1[63]} + {{13{vss}}, mux_mant[1]&qp1[63]&~exp_ovf};
|
||||
|
||||
// Overflow only occurs for double precision, if Texp[10] to Texp[0] are
|
||||
// all ones. To encourage sharing with single precision overflow detection,
|
||||
// the lower 7 bits are tested separately.
|
||||
assign Texp_l7o = Texp[6]&Texp[5]&Texp[4]&Texp[3]&Texp[2]&Texp[1]&Texp[0];
|
||||
assign OvFlow_DP = (~Texp[12]&Texp[11]) | (Texp[10]&Texp[9]&Texp[8]&Texp[7]&Texp_l7o);
|
||||
|
||||
// Overflow occurs for single precision if (Texp[10] is one) and
|
||||
// ((Texp[9] or Texp[8] or Texp[7]) is one) or (Texp[6] to Texp[0]
|
||||
// are all ones.
|
||||
assign OvFlow_SP = Texp[10]&(Texp[9]|Texp[8]|Texp[7]|Texp_l7o);
|
||||
|
||||
// Underflow occurs for double precision if (Texp[11]/Texp[10] is one) or
|
||||
// Texp[10] to Texp[0] are all zeros.
|
||||
assign Texp_l7z = ~Texp[6]&~Texp[5]&~Texp[4]&~Texp[3]&~Texp[2]&~Texp[1]&~Texp[0];
|
||||
assign UnFlow_DP = (Texp[12]&Texp[11]) | ~Texp[11]&~Texp[10]&~Texp[9]&~Texp[8]&~Texp[7]&Texp_l7z;
|
||||
|
||||
// Underflow occurs for single precision if (Texp[10] is zero) and
|
||||
// (Texp[9] or Texp[8] or Texp[7]) is zero.
|
||||
assign UnFlow_SP = ~Texp[10]&(~Texp[9]|~Texp[8]|~Texp[7]|Texp_l7z);
|
||||
|
||||
// Set the overflow and underflow flags. They should not be set if
|
||||
// the input was infinite or NaN or the output of the adder is zero.
|
||||
// 00 = Valid
|
||||
// 10 = NaN
|
||||
assign Valid = (~sel_inv[2]&~sel_inv[1]&~sel_inv[0]);
|
||||
assign NaN = ~sel_inv[1]& sel_inv[0];
|
||||
assign UnderFlow = (P & UnFlow_SP | UnFlow_DP) & Valid;
|
||||
assign OverFlow = (P & OvFlow_SP | OvFlow_DP) & Valid;
|
||||
assign Div0 = sel_inv[2]&sel_inv[1]&~sel_inv[0];
|
||||
|
||||
// The DenormIO is set if underflow has occurred or if their was a
|
||||
// denormalized input.
|
||||
assign DenormIO = DenormIn | UnderFlow;
|
||||
|
||||
// The final result is Inexact if any rounding occurred ((i.e., R or S
|
||||
// is one), or (if the result overflows ) or (if the result underflows and the
|
||||
// underflow trap is not enabled)) and (value of the result was not previous set
|
||||
// by an exception case).
|
||||
assign Inexact = (G|~zero_rem|OverFlow|(UnderFlow&~UnEn))&Valid;
|
||||
|
||||
// Set the IEEE Exception Flags: Inexact, Underflow, Overflow, Div_By_0,
|
||||
// Invlalid.
|
||||
assign Flags = {Inexact, UnderFlow, OverFlow, Div0, Invalid};
|
||||
|
||||
// Determine sign
|
||||
assign Rzero = UnderFlow | (~sel_inv[2]&sel_inv[1]&sel_inv[0]);
|
||||
assign Rsign = SignR;
|
||||
|
||||
// The exponent of the final result is zero if the final result is
|
||||
// zero or a denorm, all ones if the final result is NaN or Infinite
|
||||
// or overflow occurred and the magnitude of the number is
|
||||
// not rounded toward from zero, and all ones with an LSB of zero
|
||||
// if overflow occurred and the magnitude of the number is
|
||||
// rounded toward zero. If the result is single precision,
|
||||
// Texp[7] shoud be inverted. When the Overflow trap is enabled (OvEn = 1)
|
||||
// and overflow occurs and the operation is not conversion, bits 10 and 9 are
|
||||
// inverted for double precision, and bits 7 and 6 are inverted for single precision.
|
||||
assign Round_zero = ~rm[1]&rm[0] | ~SignR&rm[0] | SignR&rm[1]&~rm[0];
|
||||
assign VeryLarge = OverFlow & ~OvEn;
|
||||
assign Infinite = (VeryLarge & ~Round_zero) | sel_inv[1];
|
||||
assign Largest = VeryLarge & Round_zero;
|
||||
assign Adj_exp = OverFlow & OvEn;
|
||||
assign Rexp[10:1] = ({10{~Valid}} |
|
||||
{Texp[10]&~Adj_exp, Texp[9]&~Adj_exp, Texp[8],
|
||||
(Texp[7]^P)&~(Adj_exp&P), Texp[6]&~(Adj_exp&P), Texp[5:1]} |
|
||||
{10{VeryLarge}})&{10{~Rzero | NaN}};
|
||||
assign Rexp[0] = ({~Valid} | Texp[0] | Infinite)&(~Rzero | NaN)&~Largest;
|
||||
|
||||
// If the result is zero or infinity, the mantissa is all zeros.
|
||||
// If the result is NaN, the mantissa is 10...0
|
||||
// If the result the largest floating point number, the mantissa
|
||||
// is all ones. Otherwise, the mantissa is not changed.
|
||||
assign Rmant[51] = Largest | NaN | (Smant[51]&~Infinite&~Rzero);
|
||||
assign Rmant[50:0] = {51{Largest}} | (Smant[50:0]&{51{~Infinite&Valid&~Rzero}});
|
||||
|
||||
// For single precision, the 8 least significant bits of the exponent
|
||||
// and 23 most significant bits of the mantissa contain bits used
|
||||
// for the final result. A double precision result is returned if
|
||||
// overflow has occurred, the overflow trap is enabled, and a conversion
|
||||
// is being performed.
|
||||
assign OvCon = OverFlow & OvEn;
|
||||
assign Result = (P&~OvCon) ? {Rsign, Rexp[7:0], Rmant[51:29], {32{vss}}}
|
||||
: {Rsign, Rexp, Rmant};
|
||||
|
||||
endmodule // rounder
|
||||
|
||||
36
wally-pipelined/src/fpu/fpdivsqrt/run_results.sh
Executable file
36
wally-pipelined/src/fpu/fpdivsqrt/run_results.sh
Executable file
@ -0,0 +1,36 @@
|
||||
#!/bin/sh
|
||||
echo 'f64 DIV RNE' > run_results.txt
|
||||
cat f64_div_rne.out | grep '_0$' >> run_results.txt
|
||||
echo 'f64 DIV RD' >> run_results.txt
|
||||
cat f64_div_rd.out | grep '_0$' >> run_results.txt
|
||||
echo 'f64 DIV RU' >> run_results.txt
|
||||
cat f64_div_ru.out | grep '_0$' >> run_results.txt
|
||||
echo 'f64 DIV RZ' >> run_results.txt
|
||||
cat f64_div_rz.out | grep '_0$' >> run_results.txt
|
||||
|
||||
echo 'f32 DIV RNE' >> run_results.txt
|
||||
cat f32_div_rne.out | grep '_0$' >> run_results.txt
|
||||
echo 'f32 DIV RD' >> run_results.txt
|
||||
cat f32_div_rd.out | grep '_0$' >> run_results.txt
|
||||
echo 'f32 DIV RU' >> run_results.txt
|
||||
cat f32_div_ru.out | grep '_0$' >> run_results.txt
|
||||
echo 'f32 DIV RZ' >> run_results.txt
|
||||
cat f32_div_rz.out | grep '_0$' >> run_results.txt
|
||||
|
||||
echo 'f64 SQRT RNE' >> run_results.txt
|
||||
cat f64_sqrt_rne.out | grep '_0$' >> run_results.txt
|
||||
echo 'f64 SQRT RD' >> run_results.txt
|
||||
cat f64_sqrt_rd.out | grep '_0$' >> run_results.txt
|
||||
echo 'f64 SQRT RU' >> run_results.txt
|
||||
cat f64_sqrt_ru.out | grep '_0$' >> run_results.txt
|
||||
echo 'f64 SQRT RZ' >> run_results.txt
|
||||
cat f64_sqrt_rz.out | grep '_0$' >> run_results.txt
|
||||
|
||||
echo 'f32 SQRT RNE' >> run_results.txt
|
||||
cat f32_sqrt_rne.out | grep '_0$' >> run_results.txt
|
||||
echo 'f32 SQRT RD' >> run_results.txt
|
||||
cat f32_sqrt_rd.out | grep '_0$' >> run_results.txt
|
||||
echo 'f32 SQRT RU' >> run_results.txt
|
||||
cat f32_sqrt_ru.out | grep '_0$' >> run_results.txt
|
||||
echo 'f32 SQRT RZ' >> run_results.txt
|
||||
cat f32_sqrt_rz.out | grep '_0$' >> run_results.txt
|
||||
940
wally-pipelined/src/fpu/fpdivsqrt/run_results.txt
Executable file
940
wally-pipelined/src/fpu/fpdivsqrt/run_results.txt
Executable file
@ -0,0 +1,940 @@
|
||||
f64 DIV RNE
|
||||
0010000000000000_3fffffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
0010000000000000_4000000000000000_0000000000000000_11000_1 | 0008000000000000_0
|
||||
0010000000000000_4000000000000001_0000000000000000_11100_1 | 0008000000000000_0
|
||||
0010000000000000_400fffffffffffff_0000000000000000_11100_1 | 0004000000000000_0
|
||||
0010000000000000_400ffffffffffffe_0000000000000000_11100_1 | 0004000000000000_0
|
||||
0010000000000000_4010000000000000_0000000000000000_11100_1 | 0004000000000000_0
|
||||
0010000000000000_4010000000000001_0000000000000000_11000_1 | 0004000000000000_0
|
||||
0010000000000000_401fffffffffffff_0000000000000000_11000_1 | 0002000000000000_0
|
||||
0010000000000000_401ffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
0010000000000000_bfffffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
0010000000000000_c000000000000000_8000000000000000_11000_1 | 8008000000000000_0
|
||||
0010000000000000_c000000000000001_8000000000000000_11100_1 | 8008000000000000_0
|
||||
0010000000000000_c00fffffffffffff_8000000000000000_11100_1 | 8004000000000000_0
|
||||
0010000000000000_c00ffffffffffffe_8000000000000000_11100_1 | 8004000000000000_0
|
||||
0010000000000000_c010000000000000_8000000000000000_11100_1 | 8004000000000000_0
|
||||
0010000000000000_c010000000000001_8000000000000000_11000_1 | 8004000000000000_0
|
||||
0010000000000000_c01fffffffffffff_8000000000000000_11000_1 | 8002000000000000_0
|
||||
0010000000000000_c01ffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
0010000000000001_4000000000000000_0000000000000000_11000_1 | 0008000000000000_0
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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f64 DIV RD
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
001ffffffffffffe_c01ffffffffffffe_8000000000000000_11100_1 | 8004000000000000_0
|
||||
3fd0000000000000_7fe0000000000000_0000000000000000_11000_1 | 0002000000000000_0
|
||||
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|
||||
3fd0000000000000_7feffffffffffffe_0000000000000000_11000_1 | 0001000000000000_0
|
||||
3fd0000000000000_ffe0000000000000_8000000000000000_11000_1 | 8002000000000000_0
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
3fd0000000000001_ffe0000000000001_8000000000000000_11000_1 | 8002000000000000_0
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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f64 DIV RU
|
||||
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||||
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|
||||
3fd0000000000001_7feffffffffffffe_0000000000000000_11000_1 | 0001000000000000_0
|
||||
3fd0000000000001_ffe0000000000000_8000000000000000_11000_1 | 8002000000000000_0
|
||||
3fd0000000000001_ffe0000000000001_8000000000000000_11000_1 | 8002000000000000_0
|
||||
3fd0000000000001_ffefffffffffffff_8000000000000000_11000_1 | 8001000000000000_0
|
||||
3fd0000000000001_ffeffffffffffffe_8000000000000000_11000_1 | 8001000000000000_0
|
||||
3fdfffffffffffff_7fefffffffffffff_0000000000000000_11000_1 | 0002000000000000_0
|
||||
3fdfffffffffffff_7feffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
3fdfffffffffffff_ffefffffffffffff_8000000000000000_11000_1 | 8002000000000000_0
|
||||
3fdfffffffffffff_ffeffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
3fdffffffffffffe_7feffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
3fdffffffffffffe_ffeffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
3fe0000000000000_7fe0000000000000_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3fe0000000000000_7fefffffffffffff_0000000000000000_11000_1 | 0002000000000000_0
|
||||
3fe0000000000000_7feffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
3fe0000000000000_ffe0000000000000_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3fe0000000000000_ffefffffffffffff_8000000000000000_11000_1 | 8002000000000000_0
|
||||
3fe0000000000000_ffeffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
3fe0000000000001_7fe0000000000000_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3fe0000000000001_7fe0000000000001_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3fe0000000000001_7fefffffffffffff_0000000000000000_11000_1 | 0002000000000000_0
|
||||
3fe0000000000001_7feffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
3fe0000000000001_ffe0000000000000_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3fe0000000000001_ffe0000000000001_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3fe0000000000001_ffefffffffffffff_8000000000000000_11000_1 | 8002000000000000_0
|
||||
3fe0000000000001_ffeffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
3fefffffffffffff_7fefffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3fefffffffffffff_7feffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3fefffffffffffff_ffefffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3fefffffffffffff_ffeffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3feffffffffffffe_7feffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3feffffffffffffe_ffeffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3ff0000000000000_7fe0000000000000_0000000000000000_11000_1 | 0008000000000000_0
|
||||
3ff0000000000000_7fefffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3ff0000000000000_7feffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3ff0000000000000_ffe0000000000000_8000000000000000_11000_1 | 8008000000000000_0
|
||||
3ff0000000000000_ffefffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3ff0000000000000_ffeffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3ff0000000000001_7fe0000000000000_0000000000000000_11000_1 | 0008000000000000_0
|
||||
3ff0000000000001_7fe0000000000001_0000000000000000_11000_1 | 0008000000000000_0
|
||||
3ff0000000000001_7fefffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3ff0000000000001_7feffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
3ff0000000000001_ffe0000000000000_8000000000000000_11000_1 | 8008000000000000_0
|
||||
3ff0000000000001_ffe0000000000001_8000000000000000_11000_1 | 8008000000000000_0
|
||||
3ff0000000000001_ffefffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3ff0000000000001_ffeffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
3fffffffffffffff_7fefffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
3fffffffffffffff_7feffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0
|
||||
3fffffffffffffff_ffefffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
3fffffffffffffff_ffeffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0
|
||||
3ffffffffffffffe_7feffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0
|
||||
3ffffffffffffffe_ffeffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0
|
||||
4000000000000000_7fefffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
4000000000000000_7feffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0
|
||||
4000000000000000_ffefffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
4000000000000000_ffeffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0
|
||||
4000000000000001_7fefffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
4000000000000001_ffefffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
8010000000000000_3fffffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
8010000000000000_3ffffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0
|
||||
8010000000000000_4000000000000000_8000000000000000_11000_1 | 8008000000000000_0
|
||||
8010000000000000_400fffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
8010000000000000_400ffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
8010000000000000_4010000000000000_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
8010000000000000_401fffffffffffff_8000000000000000_11000_1 | 8002000000000000_0
|
||||
8010000000000000_401ffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
8010000000000000_bfffffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
8010000000000000_bffffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0
|
||||
8010000000000000_c000000000000000_0000000000000000_11000_1 | 0008000000000000_0
|
||||
8010000000000000_c00fffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
8010000000000000_c00ffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
8010000000000000_c010000000000000_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
8010000000000000_c01fffffffffffff_0000000000000000_11000_1 | 0002000000000000_0
|
||||
8010000000000000_c01ffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
8010000000000001_3fffffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
8010000000000001_4000000000000000_8000000000000000_11000_1 | 8008000000000000_0
|
||||
8010000000000001_4000000000000001_8000000000000000_11000_1 | 8008000000000000_0
|
||||
8010000000000001_400fffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
8010000000000001_400ffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
8010000000000001_4010000000000000_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
8010000000000001_4010000000000001_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
8010000000000001_401fffffffffffff_8000000000000000_11000_1 | 8002000000000000_0
|
||||
8010000000000001_401ffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
8010000000000001_bfffffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
8010000000000001_c000000000000000_0000000000000000_11000_1 | 0008000000000000_0
|
||||
8010000000000001_c000000000000001_0000000000000000_11000_1 | 0008000000000000_0
|
||||
8010000000000001_c00fffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
8010000000000001_c00ffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
8010000000000001_c010000000000000_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
8010000000000001_c010000000000001_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
8010000000000001_c01fffffffffffff_0000000000000000_11000_1 | 0002000000000000_0
|
||||
8010000000000001_c01ffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
801fffffffffffff_400fffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
801fffffffffffff_400ffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0
|
||||
801fffffffffffff_401fffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
801fffffffffffff_401ffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
801fffffffffffff_c00fffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
801fffffffffffff_c00ffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0
|
||||
801fffffffffffff_c01fffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
801fffffffffffff_c01ffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
801ffffffffffffe_400ffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0
|
||||
801ffffffffffffe_401ffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
801ffffffffffffe_c00ffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0
|
||||
801ffffffffffffe_c01ffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bfd0000000000000_7fe0000000000000_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfd0000000000000_7fefffffffffffff_8000000000000000_11000_1 | 8001000000000000_0
|
||||
bfd0000000000000_7feffffffffffffe_8000000000000000_11000_1 | 8001000000000000_0
|
||||
bfd0000000000000_ffe0000000000000_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfd0000000000000_ffefffffffffffff_0000000000000000_11000_1 | 0001000000000000_0
|
||||
bfd0000000000000_ffeffffffffffffe_0000000000000000_11000_1 | 0001000000000000_0
|
||||
bfd0000000000001_7fe0000000000000_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfd0000000000001_7fe0000000000001_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfd0000000000001_7fefffffffffffff_8000000000000000_11000_1 | 8001000000000000_0
|
||||
bfd0000000000001_7feffffffffffffe_8000000000000000_11000_1 | 8001000000000000_0
|
||||
bfd0000000000001_ffe0000000000000_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfd0000000000001_ffe0000000000001_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfd0000000000001_ffefffffffffffff_0000000000000000_11000_1 | 0001000000000000_0
|
||||
bfd0000000000001_ffeffffffffffffe_0000000000000000_11000_1 | 0001000000000000_0
|
||||
bfdfffffffffffff_7fefffffffffffff_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfdfffffffffffff_7feffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfdfffffffffffff_ffefffffffffffff_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfdfffffffffffff_ffeffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfdffffffffffffe_7feffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfdffffffffffffe_ffeffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfe0000000000000_7fe0000000000000_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bfe0000000000000_7fefffffffffffff_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfe0000000000000_7feffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfe0000000000000_ffe0000000000000_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bfe0000000000000_ffefffffffffffff_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfe0000000000000_ffeffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfe0000000000001_7fe0000000000000_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bfe0000000000001_7fe0000000000001_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bfe0000000000001_7fefffffffffffff_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfe0000000000001_7feffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0
|
||||
bfe0000000000001_ffe0000000000000_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bfe0000000000001_ffe0000000000001_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bfe0000000000001_ffefffffffffffff_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfe0000000000001_ffeffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0
|
||||
bfefffffffffffff_7fefffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bfefffffffffffff_7feffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bfefffffffffffff_ffefffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bfefffffffffffff_ffeffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bfeffffffffffffe_7feffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bfeffffffffffffe_ffeffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bff0000000000000_7fe0000000000000_8000000000000000_11000_1 | 8008000000000000_0
|
||||
bff0000000000000_7fefffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bff0000000000000_7feffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bff0000000000000_ffe0000000000000_0000000000000000_11000_1 | 0008000000000000_0
|
||||
bff0000000000000_ffefffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bff0000000000000_ffeffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bff0000000000001_7fe0000000000000_8000000000000000_11000_1 | 8008000000000000_0
|
||||
bff0000000000001_7fe0000000000001_8000000000000000_11000_1 | 8008000000000000_0
|
||||
bff0000000000001_7fefffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bff0000000000001_7feffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0
|
||||
bff0000000000001_ffe0000000000000_0000000000000000_11000_1 | 0008000000000000_0
|
||||
bff0000000000001_ffe0000000000001_0000000000000000_11000_1 | 0008000000000000_0
|
||||
bff0000000000001_ffefffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bff0000000000001_ffeffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0
|
||||
bfffffffffffffff_7fefffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
bfffffffffffffff_7feffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0
|
||||
bfffffffffffffff_ffefffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
bfffffffffffffff_ffeffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0
|
||||
bffffffffffffffe_7feffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0
|
||||
bffffffffffffffe_ffeffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0
|
||||
c000000000000000_7fefffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
c000000000000000_7feffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0
|
||||
c000000000000000_ffefffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
c000000000000000_ffeffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0
|
||||
c000000000000001_7fefffffffffffff_8000000000000000_11000_1 | 8008000000000000_0
|
||||
c000000000000001_ffefffffffffffff_0000000000000000_11000_1 | 0008000000000000_0
|
||||
f32 DIV RNE
|
||||
f32 DIV RD
|
||||
f32 DIV RU
|
||||
f32 DIV RZ
|
||||
f64 SQRT RNE
|
||||
f64 SQRT RD
|
||||
f64 SQRT RU
|
||||
f64 SQRT RZ
|
||||
f32 SQRT RNE
|
||||
f32 SQRT RD
|
||||
f32 SQRT RU
|
||||
f32 SQRT RZ
|
||||
3
wally-pipelined/src/fpu/fpdivsqrt/runme.csh
Executable file
3
wally-pipelined/src/fpu/fpdivsqrt/runme.csh
Executable file
@ -0,0 +1,3 @@
|
||||
#!/bin/sh
|
||||
vsim -do fpdiv.do -c
|
||||
tail fpdiv.out
|
||||
5
wally-pipelined/src/fpu/fpdivsqrt/runme_f32div.csh
Executable file
5
wally-pipelined/src/fpu/fpdivsqrt/runme_f32div.csh
Executable file
@ -0,0 +1,5 @@
|
||||
#!/bin/sh
|
||||
vsim -do f32_div_rne.do -c
|
||||
vsim -do f32_div_rz.do -c
|
||||
vsim -do f32_div_rd.do -c
|
||||
vsim -do f32_div_ru.do -c
|
||||
5
wally-pipelined/src/fpu/fpdivsqrt/runme_f32sqrt.csh
Executable file
5
wally-pipelined/src/fpu/fpdivsqrt/runme_f32sqrt.csh
Executable file
@ -0,0 +1,5 @@
|
||||
#!/bin/sh
|
||||
vsim -do f32_sqrt_rne.do -c
|
||||
vsim -do f32_sqrt_rz.do -c
|
||||
vsim -do f32_sqrt_rd.do -c
|
||||
vsim -do f32_sqrt_ru.do -c
|
||||
5
wally-pipelined/src/fpu/fpdivsqrt/runme_f64div.csh
Executable file
5
wally-pipelined/src/fpu/fpdivsqrt/runme_f64div.csh
Executable file
@ -0,0 +1,5 @@
|
||||
#!/bin/sh
|
||||
vsim -do f64_div_rne.do -c
|
||||
vsim -do f64_div_rz.do -c
|
||||
vsim -do f64_div_rd.do -c
|
||||
vsim -do f64_div_ru.do -c
|
||||
5
wally-pipelined/src/fpu/fpdivsqrt/runme_f64sqrt.csh
Executable file
5
wally-pipelined/src/fpu/fpdivsqrt/runme_f64sqrt.csh
Executable file
@ -0,0 +1,5 @@
|
||||
#!/bin/sh
|
||||
vsim -do f64_sqrt_rne.do -c
|
||||
vsim -do f64_sqrt_rz.do -c
|
||||
vsim -do f64_sqrt_rd.do -c
|
||||
vsim -do f64_sqrt_ru.do -c
|
||||
34
wally-pipelined/src/fpu/fpdivsqrt/sbtm.sv
Executable file
34
wally-pipelined/src/fpu/fpdivsqrt/sbtm.sv
Executable file
@ -0,0 +1,34 @@
|
||||
module sbtm (input logic [11:0] a, output logic [10:0] ia_out);
|
||||
|
||||
// bit partitions
|
||||
logic [3:0] x0;
|
||||
logic [2:0] x1;
|
||||
logic [3:0] x2;
|
||||
logic [2:0] x2_1cmp;
|
||||
// mem outputs
|
||||
logic [12:0] y0;
|
||||
logic [4:0] y1;
|
||||
// input to CPA
|
||||
logic [14:0] op1;
|
||||
logic [14:0] op2;
|
||||
logic [14:0] p;
|
||||
|
||||
assign x0 = a[10:7];
|
||||
assign x1 = a[6:4];
|
||||
assign x2 = a[3:0];
|
||||
|
||||
sbtm_a0 mem1 ({x0, x1}, y0);
|
||||
// 1s cmp per sbtm/stam
|
||||
assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0];
|
||||
sbtm_a1 mem2 ({x0, x2_1cmp}, y1);
|
||||
assign op1 = {1'b0, y0, 1'b0};
|
||||
// 1s cmp per sbtm/stam
|
||||
assign op2 = x2[3] ? {1'b1, {8{1'b1}}, ~y1, 1'b1} :
|
||||
{1'b0, 8'b0, y1, 1'b1};
|
||||
// CPA
|
||||
//bk15 cp1 (cout, p, op1, op2, 1'b0);
|
||||
adder_ip #(15) cp1 (op1, op2, 1'b0, p, cout);
|
||||
//assign ia_out = {p[14:4], {53{1'b0}}};
|
||||
assign ia_out = p[14:4];
|
||||
|
||||
endmodule // sbtm
|
||||
40
wally-pipelined/src/fpu/fpdivsqrt/sbtm3.sv
Executable file
40
wally-pipelined/src/fpu/fpdivsqrt/sbtm3.sv
Executable file
@ -0,0 +1,40 @@
|
||||
module sbtm2 (input logic [11:0] a, output logic [10:0] y);
|
||||
|
||||
// bit partitions
|
||||
logic [4:0] x0;
|
||||
logic [2:0] x1;
|
||||
logic [3:0] x2;
|
||||
logic [2:0] x2_1cmp;
|
||||
// mem outputs
|
||||
logic [13:0] y0;
|
||||
logic [5:0] y1;
|
||||
// input to CPA
|
||||
logic [14:0] op1;
|
||||
logic [14:0] op2;
|
||||
logic [14:0] p;
|
||||
|
||||
assign x0 = a[11:7];
|
||||
assign x1 = a[6:4];
|
||||
assign x2 = a[3:0];
|
||||
|
||||
sbtm_a2 mem1 ({x0, x1}, y0);
|
||||
assign op1 = {y0, 1'b0};
|
||||
|
||||
// 1s cmp per sbtm/stam
|
||||
assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0];
|
||||
sbtm_a3 mem2 ({x0, x2_1cmp}, y1);
|
||||
// 1s cmp per sbtm/stam
|
||||
assign op2 = x2[3] ? {{8{1'b1}}, ~y1, 1'b1} :
|
||||
{8'b0, y1, 1'b1};
|
||||
|
||||
// CPA
|
||||
//bk15 cp1 (cout, p, op1, op2, 1'b0);
|
||||
adder_ip #(15) cp1 (op1, op2, 1'b0, p, cout);
|
||||
assign y = p[14:4];
|
||||
|
||||
endmodule // sbtm2
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
140
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a0.sv
Executable file
140
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a0.sv
Executable file
@ -0,0 +1,140 @@
|
||||
module sbtm_a0 (input logic [6:0] a,
|
||||
output logic [12:0] y);
|
||||
always_comb
|
||||
case(a)
|
||||
7'b0000000: y = 13'b1111111100010;
|
||||
7'b0000001: y = 13'b1111110100011;
|
||||
7'b0000010: y = 13'b1111101100101;
|
||||
7'b0000011: y = 13'b1111100101000;
|
||||
7'b0000100: y = 13'b1111011101100;
|
||||
7'b0000101: y = 13'b1111010110000;
|
||||
7'b0000110: y = 13'b1111001110110;
|
||||
7'b0000111: y = 13'b1111000111100;
|
||||
7'b0001000: y = 13'b1111000000100;
|
||||
7'b0001001: y = 13'b1110111001100;
|
||||
7'b0001010: y = 13'b1110110010101;
|
||||
7'b0001011: y = 13'b1110101011110;
|
||||
7'b0001100: y = 13'b1110100101001;
|
||||
7'b0001101: y = 13'b1110011110100;
|
||||
7'b0001110: y = 13'b1110011000000;
|
||||
7'b0001111: y = 13'b1110010001101;
|
||||
7'b0010000: y = 13'b1110001011010;
|
||||
7'b0010001: y = 13'b1110000101000;
|
||||
7'b0010010: y = 13'b1101111110111;
|
||||
7'b0010011: y = 13'b1101111000110;
|
||||
7'b0010100: y = 13'b1101110010111;
|
||||
7'b0010101: y = 13'b1101101100111;
|
||||
7'b0010110: y = 13'b1101100111001;
|
||||
7'b0010111: y = 13'b1101100001011;
|
||||
7'b0011000: y = 13'b1101011011101;
|
||||
7'b0011001: y = 13'b1101010110001;
|
||||
7'b0011010: y = 13'b1101010000100;
|
||||
7'b0011011: y = 13'b1101001011001;
|
||||
7'b0011100: y = 13'b1101000101110;
|
||||
7'b0011101: y = 13'b1101000000011;
|
||||
7'b0011110: y = 13'b1100111011001;
|
||||
7'b0011111: y = 13'b1100110101111;
|
||||
7'b0100000: y = 13'b1100110000110;
|
||||
7'b0100001: y = 13'b1100101011110;
|
||||
7'b0100010: y = 13'b1100100110110;
|
||||
7'b0100011: y = 13'b1100100001111;
|
||||
7'b0100100: y = 13'b1100011101000;
|
||||
7'b0100101: y = 13'b1100011000001;
|
||||
7'b0100110: y = 13'b1100010011011;
|
||||
7'b0100111: y = 13'b1100001110101;
|
||||
7'b0101000: y = 13'b1100001010000;
|
||||
7'b0101001: y = 13'b1100000101011;
|
||||
7'b0101010: y = 13'b1100000000111;
|
||||
7'b0101011: y = 13'b1011111100011;
|
||||
7'b0101100: y = 13'b1011111000000;
|
||||
7'b0101101: y = 13'b1011110011101;
|
||||
7'b0101110: y = 13'b1011101111010;
|
||||
7'b0101111: y = 13'b1011101011000;
|
||||
7'b0110000: y = 13'b1011100110110;
|
||||
7'b0110001: y = 13'b1011100010101;
|
||||
7'b0110010: y = 13'b1011011110011;
|
||||
7'b0110011: y = 13'b1011011010011;
|
||||
7'b0110100: y = 13'b1011010110010;
|
||||
7'b0110101: y = 13'b1011010010010;
|
||||
7'b0110110: y = 13'b1011001110011;
|
||||
7'b0110111: y = 13'b1011001010011;
|
||||
7'b0111000: y = 13'b1011000110100;
|
||||
7'b0111001: y = 13'b1011000010110;
|
||||
7'b0111010: y = 13'b1010111110111;
|
||||
7'b0111011: y = 13'b1010111011001;
|
||||
7'b0111100: y = 13'b1010110111100;
|
||||
7'b0111101: y = 13'b1010110011110;
|
||||
7'b0111110: y = 13'b1010110000001;
|
||||
7'b0111111: y = 13'b1010101100100;
|
||||
7'b1000000: y = 13'b1010101001000;
|
||||
7'b1000001: y = 13'b1010100101100;
|
||||
7'b1000010: y = 13'b1010100010000;
|
||||
7'b1000011: y = 13'b1010011110100;
|
||||
7'b1000100: y = 13'b1010011011001;
|
||||
7'b1000101: y = 13'b1010010111110;
|
||||
7'b1000110: y = 13'b1010010100011;
|
||||
7'b1000111: y = 13'b1010010001001;
|
||||
7'b1001000: y = 13'b1010001101111;
|
||||
7'b1001001: y = 13'b1010001010101;
|
||||
7'b1001010: y = 13'b1010000111011;
|
||||
7'b1001011: y = 13'b1010000100001;
|
||||
7'b1001100: y = 13'b1010000001000;
|
||||
7'b1001101: y = 13'b1001111101111;
|
||||
7'b1001110: y = 13'b1001111010111;
|
||||
7'b1001111: y = 13'b1001110111110;
|
||||
7'b1010000: y = 13'b1001110100110;
|
||||
7'b1010001: y = 13'b1001110001110;
|
||||
7'b1010010: y = 13'b1001101110110;
|
||||
7'b1010011: y = 13'b1001101011111;
|
||||
7'b1010100: y = 13'b1001101000111;
|
||||
7'b1010101: y = 13'b1001100110000;
|
||||
7'b1010110: y = 13'b1001100011001;
|
||||
7'b1010111: y = 13'b1001100000010;
|
||||
7'b1011000: y = 13'b1001011101100;
|
||||
7'b1011001: y = 13'b1001011010110;
|
||||
7'b1011010: y = 13'b1001011000000;
|
||||
7'b1011011: y = 13'b1001010101010;
|
||||
7'b1011100: y = 13'b1001010010100;
|
||||
7'b1011101: y = 13'b1001001111111;
|
||||
7'b1011110: y = 13'b1001001101001;
|
||||
7'b1011111: y = 13'b1001001010100;
|
||||
7'b1100000: y = 13'b1001000111111;
|
||||
7'b1100001: y = 13'b1001000101011;
|
||||
7'b1100010: y = 13'b1001000010110;
|
||||
7'b1100011: y = 13'b1001000000010;
|
||||
7'b1100100: y = 13'b1000111101110;
|
||||
7'b1100101: y = 13'b1000111011010;
|
||||
7'b1100110: y = 13'b1000111000110;
|
||||
7'b1100111: y = 13'b1000110110010;
|
||||
7'b1101000: y = 13'b1000110011111;
|
||||
7'b1101001: y = 13'b1000110001011;
|
||||
7'b1101010: y = 13'b1000101111000;
|
||||
7'b1101011: y = 13'b1000101100101;
|
||||
7'b1101100: y = 13'b1000101010010;
|
||||
7'b1101101: y = 13'b1000101000000;
|
||||
7'b1101110: y = 13'b1000100101101;
|
||||
7'b1101111: y = 13'b1000100011011;
|
||||
7'b1110000: y = 13'b1000100001001;
|
||||
7'b1110001: y = 13'b1000011110110;
|
||||
7'b1110010: y = 13'b1000011100101;
|
||||
7'b1110011: y = 13'b1000011010011;
|
||||
7'b1110100: y = 13'b1000011000001;
|
||||
7'b1110101: y = 13'b1000010110000;
|
||||
7'b1110110: y = 13'b1000010011110;
|
||||
7'b1110111: y = 13'b1000010001101;
|
||||
7'b1111000: y = 13'b1000001111100;
|
||||
7'b1111001: y = 13'b1000001101011;
|
||||
7'b1111010: y = 13'b1000001011010;
|
||||
7'b1111011: y = 13'b1000001001010;
|
||||
7'b1111100: y = 13'b1000000111001;
|
||||
7'b1111101: y = 13'b1000000101001;
|
||||
7'b1111110: y = 13'b1000000011001;
|
||||
7'b1111111: y = 13'b1000000001001;
|
||||
default: y = 13'bxxxxxxxxxxxxx;
|
||||
endcase // case (a)
|
||||
|
||||
endmodule // sbtm_a0
|
||||
|
||||
|
||||
|
||||
|
||||
140
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a1.sv
Executable file
140
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a1.sv
Executable file
@ -0,0 +1,140 @@
|
||||
module sbtm_a1 (input logic [6:0] a,
|
||||
output logic [4:0] y);
|
||||
always_comb
|
||||
case(a)
|
||||
7'b0000000: y = 5'b11100;
|
||||
7'b0000001: y = 5'b11000;
|
||||
7'b0000010: y = 5'b10100;
|
||||
7'b0000011: y = 5'b10000;
|
||||
7'b0000100: y = 5'b01101;
|
||||
7'b0000101: y = 5'b01001;
|
||||
7'b0000110: y = 5'b00101;
|
||||
7'b0000111: y = 5'b00001;
|
||||
7'b0001000: y = 5'b11001;
|
||||
7'b0001001: y = 5'b10101;
|
||||
7'b0001010: y = 5'b10010;
|
||||
7'b0001011: y = 5'b01111;
|
||||
7'b0001100: y = 5'b01011;
|
||||
7'b0001101: y = 5'b01000;
|
||||
7'b0001110: y = 5'b00101;
|
||||
7'b0001111: y = 5'b00001;
|
||||
7'b0010000: y = 5'b10110;
|
||||
7'b0010001: y = 5'b10011;
|
||||
7'b0010010: y = 5'b10000;
|
||||
7'b0010011: y = 5'b01101;
|
||||
7'b0010100: y = 5'b01010;
|
||||
7'b0010101: y = 5'b00111;
|
||||
7'b0010110: y = 5'b00100;
|
||||
7'b0010111: y = 5'b00001;
|
||||
7'b0011000: y = 5'b10100;
|
||||
7'b0011001: y = 5'b10001;
|
||||
7'b0011010: y = 5'b01110;
|
||||
7'b0011011: y = 5'b01100;
|
||||
7'b0011100: y = 5'b01001;
|
||||
7'b0011101: y = 5'b00110;
|
||||
7'b0011110: y = 5'b00100;
|
||||
7'b0011111: y = 5'b00001;
|
||||
7'b0100000: y = 5'b10010;
|
||||
7'b0100001: y = 5'b01111;
|
||||
7'b0100010: y = 5'b01101;
|
||||
7'b0100011: y = 5'b01010;
|
||||
7'b0100100: y = 5'b01000;
|
||||
7'b0100101: y = 5'b00110;
|
||||
7'b0100110: y = 5'b00011;
|
||||
7'b0100111: y = 5'b00001;
|
||||
7'b0101000: y = 5'b10000;
|
||||
7'b0101001: y = 5'b01110;
|
||||
7'b0101010: y = 5'b01100;
|
||||
7'b0101011: y = 5'b01001;
|
||||
7'b0101100: y = 5'b00111;
|
||||
7'b0101101: y = 5'b00101;
|
||||
7'b0101110: y = 5'b00011;
|
||||
7'b0101111: y = 5'b00001;
|
||||
7'b0110000: y = 5'b01111;
|
||||
7'b0110001: y = 5'b01101;
|
||||
7'b0110010: y = 5'b01011;
|
||||
7'b0110011: y = 5'b01001;
|
||||
7'b0110100: y = 5'b00111;
|
||||
7'b0110101: y = 5'b00101;
|
||||
7'b0110110: y = 5'b00011;
|
||||
7'b0110111: y = 5'b00001;
|
||||
7'b0111000: y = 5'b01101;
|
||||
7'b0111001: y = 5'b01100;
|
||||
7'b0111010: y = 5'b01010;
|
||||
7'b0111011: y = 5'b01000;
|
||||
7'b0111100: y = 5'b00110;
|
||||
7'b0111101: y = 5'b00100;
|
||||
7'b0111110: y = 5'b00010;
|
||||
7'b0111111: y = 5'b00000;
|
||||
7'b1000000: y = 5'b01100;
|
||||
7'b1000001: y = 5'b01011;
|
||||
7'b1000010: y = 5'b01001;
|
||||
7'b1000011: y = 5'b00111;
|
||||
7'b1000100: y = 5'b00101;
|
||||
7'b1000101: y = 5'b00100;
|
||||
7'b1000110: y = 5'b00010;
|
||||
7'b1000111: y = 5'b00000;
|
||||
7'b1001000: y = 5'b01011;
|
||||
7'b1001001: y = 5'b01010;
|
||||
7'b1001010: y = 5'b01000;
|
||||
7'b1001011: y = 5'b00111;
|
||||
7'b1001100: y = 5'b00101;
|
||||
7'b1001101: y = 5'b00011;
|
||||
7'b1001110: y = 5'b00010;
|
||||
7'b1001111: y = 5'b00000;
|
||||
7'b1010000: y = 5'b01010;
|
||||
7'b1010001: y = 5'b01001;
|
||||
7'b1010010: y = 5'b01000;
|
||||
7'b1010011: y = 5'b00110;
|
||||
7'b1010100: y = 5'b00101;
|
||||
7'b1010101: y = 5'b00011;
|
||||
7'b1010110: y = 5'b00010;
|
||||
7'b1010111: y = 5'b00000;
|
||||
7'b1011000: y = 5'b01010;
|
||||
7'b1011001: y = 5'b01000;
|
||||
7'b1011010: y = 5'b00111;
|
||||
7'b1011011: y = 5'b00110;
|
||||
7'b1011100: y = 5'b00100;
|
||||
7'b1011101: y = 5'b00011;
|
||||
7'b1011110: y = 5'b00010;
|
||||
7'b1011111: y = 5'b00000;
|
||||
7'b1100000: y = 5'b01001;
|
||||
7'b1100001: y = 5'b01000;
|
||||
7'b1100010: y = 5'b00110;
|
||||
7'b1100011: y = 5'b00101;
|
||||
7'b1100100: y = 5'b00100;
|
||||
7'b1100101: y = 5'b00011;
|
||||
7'b1100110: y = 5'b00001;
|
||||
7'b1100111: y = 5'b00000;
|
||||
7'b1101000: y = 5'b01000;
|
||||
7'b1101001: y = 5'b00111;
|
||||
7'b1101010: y = 5'b00110;
|
||||
7'b1101011: y = 5'b00101;
|
||||
7'b1101100: y = 5'b00100;
|
||||
7'b1101101: y = 5'b00010;
|
||||
7'b1101110: y = 5'b00001;
|
||||
7'b1101111: y = 5'b00000;
|
||||
7'b1110000: y = 5'b01000;
|
||||
7'b1110001: y = 5'b00111;
|
||||
7'b1110010: y = 5'b00110;
|
||||
7'b1110011: y = 5'b00100;
|
||||
7'b1110100: y = 5'b00011;
|
||||
7'b1110101: y = 5'b00010;
|
||||
7'b1110110: y = 5'b00001;
|
||||
7'b1110111: y = 5'b00000;
|
||||
7'b1111000: y = 5'b00111;
|
||||
7'b1111001: y = 5'b00110;
|
||||
7'b1111010: y = 5'b00101;
|
||||
7'b1111011: y = 5'b00100;
|
||||
7'b1111100: y = 5'b00011;
|
||||
7'b1111101: y = 5'b00010;
|
||||
7'b1111110: y = 5'b00001;
|
||||
7'b1111111: y = 5'b00000;
|
||||
default: y = 5'bxxxxx;
|
||||
endcase // case (a)
|
||||
|
||||
endmodule // sbtm_a0
|
||||
|
||||
|
||||
|
||||
|
||||
140
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a2.sv
Executable file
140
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a2.sv
Executable file
@ -0,0 +1,140 @@
|
||||
module sbtm_a2 (input logic [6:0] a,
|
||||
output logic [12:0] y);
|
||||
always_comb
|
||||
case(a)
|
||||
7'b0000000: y = 13'b1111111110001;
|
||||
7'b0000001: y = 13'b1111111010001;
|
||||
7'b0000010: y = 13'b1111110110010;
|
||||
7'b0000011: y = 13'b1111110010011;
|
||||
7'b0000100: y = 13'b1111101110101;
|
||||
7'b0000101: y = 13'b1111101010110;
|
||||
7'b0000110: y = 13'b1111100111001;
|
||||
7'b0000111: y = 13'b1111100011011;
|
||||
7'b0001000: y = 13'b1111011111110;
|
||||
7'b0001001: y = 13'b1111011100001;
|
||||
7'b0001010: y = 13'b1111011000100;
|
||||
7'b0001011: y = 13'b1111010101000;
|
||||
7'b0001100: y = 13'b1111010001100;
|
||||
7'b0001101: y = 13'b1111001110000;
|
||||
7'b0001110: y = 13'b1111001010101;
|
||||
7'b0001111: y = 13'b1111000111010;
|
||||
7'b0010000: y = 13'b1111000011111;
|
||||
7'b0010001: y = 13'b1111000000100;
|
||||
7'b0010010: y = 13'b1110111101010;
|
||||
7'b0010011: y = 13'b1110111010000;
|
||||
7'b0010100: y = 13'b1110110110110;
|
||||
7'b0010101: y = 13'b1110110011101;
|
||||
7'b0010110: y = 13'b1110110000100;
|
||||
7'b0010111: y = 13'b1110101101011;
|
||||
7'b0011000: y = 13'b1110101010010;
|
||||
7'b0011001: y = 13'b1110100111001;
|
||||
7'b0011010: y = 13'b1110100100001;
|
||||
7'b0011011: y = 13'b1110100001001;
|
||||
7'b0011100: y = 13'b1110011110001;
|
||||
7'b0011101: y = 13'b1110011011010;
|
||||
7'b0011110: y = 13'b1110011000010;
|
||||
7'b0011111: y = 13'b1110010101011;
|
||||
7'b0100000: y = 13'b1110010010100;
|
||||
7'b0100001: y = 13'b1110001111110;
|
||||
7'b0100010: y = 13'b1110001100111;
|
||||
7'b0100011: y = 13'b1110001010001;
|
||||
7'b0100100: y = 13'b1110000111011;
|
||||
7'b0100101: y = 13'b1110000100101;
|
||||
7'b0100110: y = 13'b1110000001111;
|
||||
7'b0100111: y = 13'b1101111111010;
|
||||
7'b0101000: y = 13'b1101111100101;
|
||||
7'b0101001: y = 13'b1101111010000;
|
||||
7'b0101010: y = 13'b1101110111011;
|
||||
7'b0101011: y = 13'b1101110100110;
|
||||
7'b0101100: y = 13'b1101110010001;
|
||||
7'b0101101: y = 13'b1101101111101;
|
||||
7'b0101110: y = 13'b1101101101001;
|
||||
7'b0101111: y = 13'b1101101010101;
|
||||
7'b0110000: y = 13'b1101101000001;
|
||||
7'b0110001: y = 13'b1101100101101;
|
||||
7'b0110010: y = 13'b1101100011010;
|
||||
7'b0110011: y = 13'b1101100000110;
|
||||
7'b0110100: y = 13'b1101011110011;
|
||||
7'b0110101: y = 13'b1101011100000;
|
||||
7'b0110110: y = 13'b1101011001101;
|
||||
7'b0110111: y = 13'b1101010111010;
|
||||
7'b0111000: y = 13'b1101010101000;
|
||||
7'b0111001: y = 13'b1101010010101;
|
||||
7'b0111010: y = 13'b1101010000011;
|
||||
7'b0111011: y = 13'b1101001110001;
|
||||
7'b0111100: y = 13'b1101001011111;
|
||||
7'b0111101: y = 13'b1101001001101;
|
||||
7'b0111110: y = 13'b1101000111100;
|
||||
7'b0111111: y = 13'b1101000101010;
|
||||
7'b1000000: y = 13'b1101000011001;
|
||||
7'b1000001: y = 13'b1101000000111;
|
||||
7'b1000010: y = 13'b1100111110110;
|
||||
7'b1000011: y = 13'b1100111100101;
|
||||
7'b1000100: y = 13'b1100111010100;
|
||||
7'b1000101: y = 13'b1100111000011;
|
||||
7'b1000110: y = 13'b1100110110011;
|
||||
7'b1000111: y = 13'b1100110100010;
|
||||
7'b1001000: y = 13'b1100110010010;
|
||||
7'b1001001: y = 13'b1100110000010;
|
||||
7'b1001010: y = 13'b1100101110010;
|
||||
7'b1001011: y = 13'b1100101100001;
|
||||
7'b1001100: y = 13'b1100101010010;
|
||||
7'b1001101: y = 13'b1100101000010;
|
||||
7'b1001110: y = 13'b1100100110010;
|
||||
7'b1001111: y = 13'b1100100100011;
|
||||
7'b1010000: y = 13'b1100100010011;
|
||||
7'b1010001: y = 13'b1100100000100;
|
||||
7'b1010010: y = 13'b1100011110101;
|
||||
7'b1010011: y = 13'b1100011100101;
|
||||
7'b1010100: y = 13'b1100011010110;
|
||||
7'b1010101: y = 13'b1100011000111;
|
||||
7'b1010110: y = 13'b1100010111001;
|
||||
7'b1010111: y = 13'b1100010101010;
|
||||
7'b1011000: y = 13'b1100010011011;
|
||||
7'b1011001: y = 13'b1100010001101;
|
||||
7'b1011010: y = 13'b1100001111110;
|
||||
7'b1011011: y = 13'b1100001110000;
|
||||
7'b1011100: y = 13'b1100001100010;
|
||||
7'b1011101: y = 13'b1100001010100;
|
||||
7'b1011110: y = 13'b1100001000110;
|
||||
7'b1011111: y = 13'b1100000111000;
|
||||
7'b1100000: y = 13'b1100000101010;
|
||||
7'b1100001: y = 13'b1100000011100;
|
||||
7'b1100010: y = 13'b1100000001111;
|
||||
7'b1100011: y = 13'b1100000000001;
|
||||
7'b1100100: y = 13'b1011111110100;
|
||||
7'b1100101: y = 13'b1011111100110;
|
||||
7'b1100110: y = 13'b1011111011001;
|
||||
7'b1100111: y = 13'b1011111001100;
|
||||
7'b1101000: y = 13'b1011110111111;
|
||||
7'b1101001: y = 13'b1011110110010;
|
||||
7'b1101010: y = 13'b1011110100101;
|
||||
7'b1101011: y = 13'b1011110011000;
|
||||
7'b1101100: y = 13'b1011110001011;
|
||||
7'b1101101: y = 13'b1011101111110;
|
||||
7'b1101110: y = 13'b1011101110010;
|
||||
7'b1101111: y = 13'b1011101100101;
|
||||
7'b1110000: y = 13'b1011101011001;
|
||||
7'b1110001: y = 13'b1011101001100;
|
||||
7'b1110010: y = 13'b1011101000000;
|
||||
7'b1110011: y = 13'b1011100110100;
|
||||
7'b1110100: y = 13'b1011100101000;
|
||||
7'b1110101: y = 13'b1011100011100;
|
||||
7'b1110110: y = 13'b1011100010000;
|
||||
7'b1110111: y = 13'b1011100000100;
|
||||
7'b1111000: y = 13'b1011011111000;
|
||||
7'b1111001: y = 13'b1011011101100;
|
||||
7'b1111010: y = 13'b1011011100000;
|
||||
7'b1111011: y = 13'b1011011010101;
|
||||
7'b1111100: y = 13'b1011011001001;
|
||||
7'b1111101: y = 13'b1011010111101;
|
||||
7'b1111110: y = 13'b1011010110010;
|
||||
7'b1111111: y = 13'b1011010100111;
|
||||
default: y = 13'bxxxxxxxxxxxxx;
|
||||
endcase // case (a)
|
||||
|
||||
endmodule // sbtm_a0
|
||||
|
||||
|
||||
|
||||
|
||||
204
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a4.sv
Executable file
204
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a4.sv
Executable file
@ -0,0 +1,204 @@
|
||||
module sbtm_a2 (input logic [7:0] a,
|
||||
output logic [13:0] y);
|
||||
always_comb
|
||||
case(a)
|
||||
8'b01000000: y = 14'b10110100010111;
|
||||
8'b01000001: y = 14'b10110010111111;
|
||||
8'b01000010: y = 14'b10110001101000;
|
||||
8'b01000011: y = 14'b10110000010011;
|
||||
8'b01000100: y = 14'b10101111000001;
|
||||
8'b01000101: y = 14'b10101101110000;
|
||||
8'b01000110: y = 14'b10101100100001;
|
||||
8'b01000111: y = 14'b10101011010011;
|
||||
8'b01001000: y = 14'b10101010000111;
|
||||
8'b01001001: y = 14'b10101000111101;
|
||||
8'b01001010: y = 14'b10100111110100;
|
||||
8'b01001011: y = 14'b10100110101101;
|
||||
8'b01001100: y = 14'b10100101100111;
|
||||
8'b01001101: y = 14'b10100100100010;
|
||||
8'b01001110: y = 14'b10100011011111;
|
||||
8'b01001111: y = 14'b10100010011101;
|
||||
8'b01010000: y = 14'b10100001011100;
|
||||
8'b01010001: y = 14'b10100000011100;
|
||||
8'b01010010: y = 14'b10011111011110;
|
||||
8'b01010011: y = 14'b10011110100001;
|
||||
8'b01010100: y = 14'b10011101100100;
|
||||
8'b01010101: y = 14'b10011100101001;
|
||||
8'b01010110: y = 14'b10011011101111;
|
||||
8'b01010111: y = 14'b10011010110110;
|
||||
8'b01011000: y = 14'b10011001111110;
|
||||
8'b01011001: y = 14'b10011001000110;
|
||||
8'b01011010: y = 14'b10011000010000;
|
||||
8'b01011011: y = 14'b10010111011011;
|
||||
8'b01011100: y = 14'b10010110100110;
|
||||
8'b01011101: y = 14'b10010101110011;
|
||||
8'b01011110: y = 14'b10010101000000;
|
||||
8'b01011111: y = 14'b10010100001110;
|
||||
8'b01100000: y = 14'b10010011011100;
|
||||
8'b01100001: y = 14'b10010010101100;
|
||||
8'b01100010: y = 14'b10010001111100;
|
||||
8'b01100011: y = 14'b10010001001101;
|
||||
8'b01100100: y = 14'b10010000011111;
|
||||
8'b01100101: y = 14'b10001111110001;
|
||||
8'b01100110: y = 14'b10001111000100;
|
||||
8'b01100111: y = 14'b10001110011000;
|
||||
8'b01101000: y = 14'b10001101101100;
|
||||
8'b01101001: y = 14'b10001101000001;
|
||||
8'b01101010: y = 14'b10001100010110;
|
||||
8'b01101011: y = 14'b10001011101100;
|
||||
8'b01101100: y = 14'b10001011000011;
|
||||
8'b01101101: y = 14'b10001010011010;
|
||||
8'b01101110: y = 14'b10001001110010;
|
||||
8'b01101111: y = 14'b10001001001010;
|
||||
8'b01110000: y = 14'b10001000100011;
|
||||
8'b01110001: y = 14'b10000111111101;
|
||||
8'b01110010: y = 14'b10000111010111;
|
||||
8'b01110011: y = 14'b10000110110001;
|
||||
8'b01110100: y = 14'b10000110001100;
|
||||
8'b01110101: y = 14'b10000101100111;
|
||||
8'b01110110: y = 14'b10000101000011;
|
||||
8'b01110111: y = 14'b10000100011111;
|
||||
8'b01111000: y = 14'b10000011111100;
|
||||
8'b01111001: y = 14'b10000011011001;
|
||||
8'b01111010: y = 14'b10000010110111;
|
||||
8'b01111011: y = 14'b10000010010101;
|
||||
8'b01111100: y = 14'b10000001110011;
|
||||
8'b01111101: y = 14'b10000001010010;
|
||||
8'b01111110: y = 14'b10000000110001;
|
||||
8'b01111111: y = 14'b10000000010001;
|
||||
8'b10000000: y = 14'b01111111110001;
|
||||
8'b10000001: y = 14'b01111111010001;
|
||||
8'b10000010: y = 14'b01111110110010;
|
||||
8'b10000011: y = 14'b01111110010011;
|
||||
8'b10000100: y = 14'b01111101110101;
|
||||
8'b10000101: y = 14'b01111101010110;
|
||||
8'b10000110: y = 14'b01111100111001;
|
||||
8'b10000111: y = 14'b01111100011011;
|
||||
8'b10001000: y = 14'b01111011111110;
|
||||
8'b10001001: y = 14'b01111011100001;
|
||||
8'b10001010: y = 14'b01111011000100;
|
||||
8'b10001011: y = 14'b01111010101000;
|
||||
8'b10001100: y = 14'b01111010001100;
|
||||
8'b10001101: y = 14'b01111001110000;
|
||||
8'b10001110: y = 14'b01111001010101;
|
||||
8'b10001111: y = 14'b01111000111010;
|
||||
8'b10010000: y = 14'b01111000011111;
|
||||
8'b10010001: y = 14'b01111000000100;
|
||||
8'b10010010: y = 14'b01110111101010;
|
||||
8'b10010011: y = 14'b01110111010000;
|
||||
8'b10010100: y = 14'b01110110110110;
|
||||
8'b10010101: y = 14'b01110110011101;
|
||||
8'b10010110: y = 14'b01110110000100;
|
||||
8'b10010111: y = 14'b01110101101011;
|
||||
8'b10011000: y = 14'b01110101010010;
|
||||
8'b10011001: y = 14'b01110100111001;
|
||||
8'b10011010: y = 14'b01110100100001;
|
||||
8'b10011011: y = 14'b01110100001001;
|
||||
8'b10011100: y = 14'b01110011110001;
|
||||
8'b10011101: y = 14'b01110011011010;
|
||||
8'b10011110: y = 14'b01110011000010;
|
||||
8'b10011111: y = 14'b01110010101011;
|
||||
8'b10100000: y = 14'b01110010010100;
|
||||
8'b10100001: y = 14'b01110001111110;
|
||||
8'b10100010: y = 14'b01110001100111;
|
||||
8'b10100011: y = 14'b01110001010001;
|
||||
8'b10100100: y = 14'b01110000111011;
|
||||
8'b10100101: y = 14'b01110000100101;
|
||||
8'b10100110: y = 14'b01110000001111;
|
||||
8'b10100111: y = 14'b01101111111010;
|
||||
8'b10101000: y = 14'b01101111100101;
|
||||
8'b10101001: y = 14'b01101111010000;
|
||||
8'b10101010: y = 14'b01101110111011;
|
||||
8'b10101011: y = 14'b01101110100110;
|
||||
8'b10101100: y = 14'b01101110010001;
|
||||
8'b10101101: y = 14'b01101101111101;
|
||||
8'b10101110: y = 14'b01101101101001;
|
||||
8'b10101111: y = 14'b01101101010101;
|
||||
8'b10110000: y = 14'b01101101000001;
|
||||
8'b10110001: y = 14'b01101100101101;
|
||||
8'b10110010: y = 14'b01101100011010;
|
||||
8'b10110011: y = 14'b01101100000110;
|
||||
8'b10110100: y = 14'b01101011110011;
|
||||
8'b10110101: y = 14'b01101011100000;
|
||||
8'b10110110: y = 14'b01101011001101;
|
||||
8'b10110111: y = 14'b01101010111010;
|
||||
8'b10111000: y = 14'b01101010101000;
|
||||
8'b10111001: y = 14'b01101010010101;
|
||||
8'b10111010: y = 14'b01101010000011;
|
||||
8'b10111011: y = 14'b01101001110001;
|
||||
8'b10111100: y = 14'b01101001011111;
|
||||
8'b10111101: y = 14'b01101001001101;
|
||||
8'b10111110: y = 14'b01101000111100;
|
||||
8'b10111111: y = 14'b01101000101010;
|
||||
8'b11000000: y = 14'b01101000011001;
|
||||
8'b11000001: y = 14'b01101000000111;
|
||||
8'b11000010: y = 14'b01100111110110;
|
||||
8'b11000011: y = 14'b01100111100101;
|
||||
8'b11000100: y = 14'b01100111010100;
|
||||
8'b11000101: y = 14'b01100111000011;
|
||||
8'b11000110: y = 14'b01100110110011;
|
||||
8'b11000111: y = 14'b01100110100010;
|
||||
8'b11001000: y = 14'b01100110010010;
|
||||
8'b11001001: y = 14'b01100110000010;
|
||||
8'b11001010: y = 14'b01100101110010;
|
||||
8'b11001011: y = 14'b01100101100001;
|
||||
8'b11001100: y = 14'b01100101010010;
|
||||
8'b11001101: y = 14'b01100101000010;
|
||||
8'b11001110: y = 14'b01100100110010;
|
||||
8'b11001111: y = 14'b01100100100011;
|
||||
8'b11010000: y = 14'b01100100010011;
|
||||
8'b11010001: y = 14'b01100100000100;
|
||||
8'b11010010: y = 14'b01100011110101;
|
||||
8'b11010011: y = 14'b01100011100101;
|
||||
8'b11010100: y = 14'b01100011010110;
|
||||
8'b11010101: y = 14'b01100011000111;
|
||||
8'b11010110: y = 14'b01100010111001;
|
||||
8'b11010111: y = 14'b01100010101010;
|
||||
8'b11011000: y = 14'b01100010011011;
|
||||
8'b11011001: y = 14'b01100010001101;
|
||||
8'b11011010: y = 14'b01100001111110;
|
||||
8'b11011011: y = 14'b01100001110000;
|
||||
8'b11011100: y = 14'b01100001100010;
|
||||
8'b11011101: y = 14'b01100001010100;
|
||||
8'b11011110: y = 14'b01100001000110;
|
||||
8'b11011111: y = 14'b01100000111000;
|
||||
8'b11100000: y = 14'b01100000101010;
|
||||
8'b11100001: y = 14'b01100000011100;
|
||||
8'b11100010: y = 14'b01100000001111;
|
||||
8'b11100011: y = 14'b01100000000001;
|
||||
8'b11100100: y = 14'b01011111110100;
|
||||
8'b11100101: y = 14'b01011111100110;
|
||||
8'b11100110: y = 14'b01011111011001;
|
||||
8'b11100111: y = 14'b01011111001100;
|
||||
8'b11101000: y = 14'b01011110111111;
|
||||
8'b11101001: y = 14'b01011110110010;
|
||||
8'b11101010: y = 14'b01011110100101;
|
||||
8'b11101011: y = 14'b01011110011000;
|
||||
8'b11101100: y = 14'b01011110001011;
|
||||
8'b11101101: y = 14'b01011101111110;
|
||||
8'b11101110: y = 14'b01011101110010;
|
||||
8'b11101111: y = 14'b01011101100101;
|
||||
8'b11110000: y = 14'b01011101011001;
|
||||
8'b11110001: y = 14'b01011101001100;
|
||||
8'b11110010: y = 14'b01011101000000;
|
||||
8'b11110011: y = 14'b01011100110100;
|
||||
8'b11110100: y = 14'b01011100101000;
|
||||
8'b11110101: y = 14'b01011100011100;
|
||||
8'b11110110: y = 14'b01011100010000;
|
||||
8'b11110111: y = 14'b01011100000100;
|
||||
8'b11111000: y = 14'b01011011111000;
|
||||
8'b11111001: y = 14'b01011011101100;
|
||||
8'b11111010: y = 14'b01011011100000;
|
||||
8'b11111011: y = 14'b01011011010101;
|
||||
8'b11111100: y = 14'b01011011001001;
|
||||
8'b11111101: y = 14'b01011010111101;
|
||||
8'b11111110: y = 14'b01011010110010;
|
||||
8'b11111111: y = 14'b01011010100111;
|
||||
default: y = 14'bxxxxxxxxxxxxxx;
|
||||
endcase // case (a)
|
||||
|
||||
endmodule // sbtm_a0
|
||||
|
||||
|
||||
|
||||
|
||||
200
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a5.sv
Executable file
200
wally-pipelined/src/fpu/fpdivsqrt/sbtm_a5.sv
Executable file
@ -0,0 +1,200 @@
|
||||
module sbtm_a3 (input logic [7:0] a,
|
||||
output logic [5:0] y);
|
||||
always_comb
|
||||
case(a)
|
||||
8'b01000000: y = 6'b100110;
|
||||
8'b01000001: y = 6'b100001;
|
||||
8'b01000010: y = 6'b011100;
|
||||
8'b01000011: y = 6'b010111;
|
||||
8'b01000100: y = 6'b010010;
|
||||
8'b01000101: y = 6'b001100;
|
||||
8'b01000110: y = 6'b000111;
|
||||
8'b01000111: y = 6'b000010;
|
||||
8'b01001000: y = 6'b100000;
|
||||
8'b01001001: y = 6'b011100;
|
||||
8'b01001010: y = 6'b011000;
|
||||
8'b01001011: y = 6'b010011;
|
||||
8'b01001100: y = 6'b001111;
|
||||
8'b01001101: y = 6'b001010;
|
||||
8'b01001110: y = 6'b000110;
|
||||
8'b01001111: y = 6'b000010;
|
||||
8'b01010000: y = 6'b011100;
|
||||
8'b01010001: y = 6'b011000;
|
||||
8'b01010010: y = 6'b010100;
|
||||
8'b01010011: y = 6'b010000;
|
||||
8'b01010100: y = 6'b001101;
|
||||
8'b01010101: y = 6'b001001;
|
||||
8'b01010110: y = 6'b000101;
|
||||
8'b01010111: y = 6'b000001;
|
||||
8'b01011000: y = 6'b011000;
|
||||
8'b01011001: y = 6'b010101;
|
||||
8'b01011010: y = 6'b010010;
|
||||
8'b01011011: y = 6'b001110;
|
||||
8'b01011100: y = 6'b001011;
|
||||
8'b01011101: y = 6'b001000;
|
||||
8'b01011110: y = 6'b000100;
|
||||
8'b01011111: y = 6'b000001;
|
||||
8'b01100000: y = 6'b010101;
|
||||
8'b01100001: y = 6'b010010;
|
||||
8'b01100010: y = 6'b001111;
|
||||
8'b01100011: y = 6'b001101;
|
||||
8'b01100100: y = 6'b001010;
|
||||
8'b01100101: y = 6'b000111;
|
||||
8'b01100110: y = 6'b000100;
|
||||
8'b01100111: y = 6'b000001;
|
||||
8'b01101000: y = 6'b010011;
|
||||
8'b01101001: y = 6'b010000;
|
||||
8'b01101010: y = 6'b001110;
|
||||
8'b01101011: y = 6'b001011;
|
||||
8'b01101100: y = 6'b001001;
|
||||
8'b01101101: y = 6'b000110;
|
||||
8'b01101110: y = 6'b000011;
|
||||
8'b01101111: y = 6'b000001;
|
||||
8'b01110000: y = 6'b010001;
|
||||
8'b01110001: y = 6'b001111;
|
||||
8'b01110010: y = 6'b001100;
|
||||
8'b01110011: y = 6'b001010;
|
||||
8'b01110100: y = 6'b001000;
|
||||
8'b01110101: y = 6'b000101;
|
||||
8'b01110110: y = 6'b000011;
|
||||
8'b01110111: y = 6'b000001;
|
||||
8'b01111000: y = 6'b001111;
|
||||
8'b01111001: y = 6'b001101;
|
||||
8'b01111010: y = 6'b001011;
|
||||
8'b01111011: y = 6'b001001;
|
||||
8'b01111100: y = 6'b000111;
|
||||
8'b01111101: y = 6'b000101;
|
||||
8'b01111110: y = 6'b000011;
|
||||
8'b01111111: y = 6'b000001;
|
||||
8'b10000000: y = 6'b001110;
|
||||
8'b10000001: y = 6'b001100;
|
||||
8'b10000010: y = 6'b001010;
|
||||
8'b10000011: y = 6'b001000;
|
||||
8'b10000100: y = 6'b000110;
|
||||
8'b10000101: y = 6'b000100;
|
||||
8'b10000110: y = 6'b000010;
|
||||
8'b10000111: y = 6'b000000;
|
||||
8'b10001000: y = 6'b001101;
|
||||
8'b10001001: y = 6'b001011;
|
||||
8'b10001010: y = 6'b001001;
|
||||
8'b10001011: y = 6'b000111;
|
||||
8'b10001100: y = 6'b000110;
|
||||
8'b10001101: y = 6'b000100;
|
||||
8'b10001110: y = 6'b000010;
|
||||
8'b10001111: y = 6'b000000;
|
||||
8'b10010000: y = 6'b001100;
|
||||
8'b10010001: y = 6'b001010;
|
||||
8'b10010010: y = 6'b001000;
|
||||
8'b10010011: y = 6'b000111;
|
||||
8'b10010100: y = 6'b000101;
|
||||
8'b10010101: y = 6'b000100;
|
||||
8'b10010110: y = 6'b000010;
|
||||
8'b10010111: y = 6'b000000;
|
||||
8'b10011000: y = 6'b001011;
|
||||
8'b10011001: y = 6'b001001;
|
||||
8'b10011010: y = 6'b001000;
|
||||
8'b10011011: y = 6'b000110;
|
||||
8'b10011100: y = 6'b000101;
|
||||
8'b10011101: y = 6'b000011;
|
||||
8'b10011110: y = 6'b000010;
|
||||
8'b10011111: y = 6'b000000;
|
||||
8'b10100000: y = 6'b001010;
|
||||
8'b10100001: y = 6'b001000;
|
||||
8'b10100010: y = 6'b000111;
|
||||
8'b10100011: y = 6'b000110;
|
||||
8'b10100100: y = 6'b000100;
|
||||
8'b10100101: y = 6'b000011;
|
||||
8'b10100110: y = 6'b000010;
|
||||
8'b10100111: y = 6'b000000;
|
||||
8'b10101000: y = 6'b001001;
|
||||
8'b10101001: y = 6'b001000;
|
||||
8'b10101010: y = 6'b000111;
|
||||
8'b10101011: y = 6'b000101;
|
||||
8'b10101100: y = 6'b000100;
|
||||
8'b10101101: y = 6'b000011;
|
||||
8'b10101110: y = 6'b000001;
|
||||
8'b10101111: y = 6'b000000;
|
||||
8'b10110000: y = 6'b001000;
|
||||
8'b10110001: y = 6'b000111;
|
||||
8'b10110010: y = 6'b000110;
|
||||
8'b10110011: y = 6'b000101;
|
||||
8'b10110100: y = 6'b000100;
|
||||
8'b10110101: y = 6'b000010;
|
||||
8'b10110110: y = 6'b000001;
|
||||
8'b10110111: y = 6'b000000;
|
||||
8'b10111000: y = 6'b001000;
|
||||
8'b10111001: y = 6'b000111;
|
||||
8'b10111010: y = 6'b000110;
|
||||
8'b10111011: y = 6'b000101;
|
||||
8'b10111100: y = 6'b000011;
|
||||
8'b10111101: y = 6'b000010;
|
||||
8'b10111110: y = 6'b000001;
|
||||
8'b10111111: y = 6'b000000;
|
||||
8'b11000000: y = 6'b000111;
|
||||
8'b11000001: y = 6'b000110;
|
||||
8'b11000010: y = 6'b000101;
|
||||
8'b11000011: y = 6'b000100;
|
||||
8'b11000100: y = 6'b000011;
|
||||
8'b11000101: y = 6'b000010;
|
||||
8'b11000110: y = 6'b000001;
|
||||
8'b11000111: y = 6'b000000;
|
||||
8'b11001000: y = 6'b000111;
|
||||
8'b11001001: y = 6'b000110;
|
||||
8'b11001010: y = 6'b000101;
|
||||
8'b11001011: y = 6'b000100;
|
||||
8'b11001100: y = 6'b000011;
|
||||
8'b11001101: y = 6'b000010;
|
||||
8'b11001110: y = 6'b000001;
|
||||
8'b11001111: y = 6'b000000;
|
||||
8'b11010000: y = 6'b000111;
|
||||
8'b11010001: y = 6'b000110;
|
||||
8'b11010010: y = 6'b000101;
|
||||
8'b11010011: y = 6'b000100;
|
||||
8'b11010100: y = 6'b000011;
|
||||
8'b11010101: y = 6'b000010;
|
||||
8'b11010110: y = 6'b000001;
|
||||
8'b11010111: y = 6'b000000;
|
||||
8'b11011000: y = 6'b000110;
|
||||
8'b11011001: y = 6'b000101;
|
||||
8'b11011010: y = 6'b000100;
|
||||
8'b11011011: y = 6'b000011;
|
||||
8'b11011100: y = 6'b000011;
|
||||
8'b11011101: y = 6'b000010;
|
||||
8'b11011110: y = 6'b000001;
|
||||
8'b11011111: y = 6'b000000;
|
||||
8'b11100000: y = 6'b000110;
|
||||
8'b11100001: y = 6'b000101;
|
||||
8'b11100010: y = 6'b000100;
|
||||
8'b11100011: y = 6'b000011;
|
||||
8'b11100100: y = 6'b000010;
|
||||
8'b11100101: y = 6'b000010;
|
||||
8'b11100110: y = 6'b000001;
|
||||
8'b11100111: y = 6'b000000;
|
||||
8'b11101000: y = 6'b000101;
|
||||
8'b11101001: y = 6'b000101;
|
||||
8'b11101010: y = 6'b000100;
|
||||
8'b11101011: y = 6'b000011;
|
||||
8'b11101100: y = 6'b000010;
|
||||
8'b11101101: y = 6'b000001;
|
||||
8'b11101110: y = 6'b000001;
|
||||
8'b11101111: y = 6'b000000;
|
||||
8'b11110000: y = 6'b000101;
|
||||
8'b11110001: y = 6'b000100;
|
||||
8'b11110010: y = 6'b000100;
|
||||
8'b11110011: y = 6'b000011;
|
||||
8'b11110100: y = 6'b000010;
|
||||
8'b11110101: y = 6'b000001;
|
||||
8'b11110110: y = 6'b000001;
|
||||
8'b11110111: y = 6'b000000;
|
||||
8'b11111000: y = 6'b000101;
|
||||
8'b11111001: y = 6'b000100;
|
||||
8'b11111010: y = 6'b000011;
|
||||
8'b11111011: y = 6'b000011;
|
||||
8'b11111100: y = 6'b000010;
|
||||
8'b11111101: y = 6'b000001;
|
||||
8'b11111110: y = 6'b000001;
|
||||
8'b11111111: y = 6'b000000;
|
||||
default: y = 6'bxxxxxx;
|
||||
endcase // case (a)
|
||||
|
||||
endmodule // sbtm_a0
|
||||
6
wally-pipelined/src/fpu/fpdivsqrt/sim.csh
Executable file
6
wally-pipelined/src/fpu/fpdivsqrt/sim.csh
Executable file
@ -0,0 +1,6 @@
|
||||
#!/bin/sh
|
||||
./runme_f64div.csh
|
||||
./runme_f32div.csh
|
||||
./runme_f64sqrt_csh
|
||||
./runme_f32sqrt.csh
|
||||
echo "Simulation Ended, Go Pokes!..."
|
||||
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rd.sv
Executable file
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rd.sv
Executable file
@ -0,0 +1,83 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [31:0] op1;
|
||||
logic [31:0] op2;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [31:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [103:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f32_div_rd.out");
|
||||
$readmemh("f32_div_rd.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b0;
|
||||
#0 P = 1'b1;
|
||||
#0 rm = 2'b11;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (11)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 31605) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rne.sv
Executable file
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rne.sv
Executable file
@ -0,0 +1,83 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [31:0] op1;
|
||||
logic [31:0] op2;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [31:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [103:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f32_div_rne.out");
|
||||
$readmemh("f32_div_rne.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b0;
|
||||
#0 P = 1'b1;
|
||||
#0 rm = 2'b00;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (11)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 31743) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_ru.sv
Executable file
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_ru.sv
Executable file
@ -0,0 +1,83 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [31:0] op1;
|
||||
logic [31:0] op2;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [31:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [103:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f32_div_ru.out");
|
||||
$readmemh("f32_div_ru.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b0;
|
||||
#0 P = 1'b1;
|
||||
#0 rm = 2'b10;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (11)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 31614) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rz.sv
Executable file
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rz.sv
Executable file
@ -0,0 +1,83 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [31:0] op1;
|
||||
logic [31:0] op2;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [31:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [103:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f32_div_rz.out");
|
||||
$readmemh("f32_div_rz.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b0;
|
||||
#0 P = 1'b1;
|
||||
#0 rm = 2'b01;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (11)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 31792) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rd.sv
Executable file
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rd.sv
Executable file
@ -0,0 +1,80 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [31:0] op1;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [31:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [71:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f32_sqrt_rd.out");
|
||||
$readmemh("f32_sqrt_rd.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b1;
|
||||
#0 P = 1'b1;
|
||||
#0 rm = 2'b11;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (16)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 19538) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rne.sv
Executable file
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rne.sv
Executable file
@ -0,0 +1,80 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [31:0] op1;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [31:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [71:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f32_sqrt_rne.out");
|
||||
$readmemh("f32_sqrt_rne.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b1;
|
||||
#0 P = 1'b1;
|
||||
#0 rm = 2'b00;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (16)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 19538) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_ru.sv
Executable file
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_ru.sv
Executable file
@ -0,0 +1,80 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [31:0] op1;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [31:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [71:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f32_sqrt_ru.out");
|
||||
$readmemh("f32_sqrt_ru.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b1;
|
||||
#0 P = 1'b1;
|
||||
#0 rm = 2'b10;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (16)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 19538) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rz.sv
Executable file
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rz.sv
Executable file
@ -0,0 +1,80 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [31:0] op1;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [31:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [71:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f32_sqrt_rz.out");
|
||||
$readmemh("f32_sqrt_rz.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b1;
|
||||
#0 P = 1'b1;
|
||||
#0 rm = 2'b01;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (16)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 19538) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rd.sv
Executable file
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rd.sv
Executable file
@ -0,0 +1,83 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [63:0] op1;
|
||||
logic [63:0] op2;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [63:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [199:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f64_div_rd.out");
|
||||
$readmemh("f64_div_rd.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b0;
|
||||
#0 P = 1'b0;
|
||||
#0 rm = 2'b11;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (13)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 39050) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
84
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rne.sv
Executable file
84
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rne.sv
Executable file
@ -0,0 +1,84 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [63:0] op1;
|
||||
logic [63:0] op2;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [63:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [199:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer handle4;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f64_div_rne.out");
|
||||
$readmemh("f64_div_rne.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b0;
|
||||
#0 P = 1'b0;
|
||||
#0 rm = 2'b00;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (13)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 39509) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_ru.sv
Executable file
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_ru.sv
Executable file
@ -0,0 +1,83 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [63:0] op1;
|
||||
logic [63:0] op2;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [63:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [199:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f64_div_ru.out");
|
||||
$readmemh("f64_div_ru.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b0;
|
||||
#0 P = 1'b0;
|
||||
#0 rm = 2'b10;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (13)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 39020) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rz.sv
Executable file
83
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rz.sv
Executable file
@ -0,0 +1,83 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [63:0] op1;
|
||||
logic [63:0] op2;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [63:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [199:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f64_div_rz.out");
|
||||
$readmemh("f64_div_rz.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b0;
|
||||
#0 P = 1'b0;
|
||||
#0 rm = 2'b01;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (13)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 39515) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rd.sv
Executable file
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rd.sv
Executable file
@ -0,0 +1,80 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [63:0] op1;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [63:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [135:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f64_sqrt_rd.out");
|
||||
$readmemh("f64_sqrt_rd.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b1;
|
||||
#0 P = 1'b0;
|
||||
#0 rm = 2'b11;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (20)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 363) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
82
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rne.sv
Executable file
82
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rne.sv
Executable file
@ -0,0 +1,82 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [63:0] op1;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [63:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [135:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f64_sqrt_rne.out");
|
||||
$readmemh("f64_sqrt_rne.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b1;
|
||||
#0 P = 1'b0;
|
||||
#0 rm = 2'b00;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (20)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 363) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_ru.sv
Executable file
80
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_ru.sv
Executable file
@ -0,0 +1,80 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [63:0] op1;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [63:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [135:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f64_sqrt_ru.out");
|
||||
$readmemh("f64_sqrt_ru.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b1;
|
||||
#0 P = 1'b0;
|
||||
#0 rm = 2'b10;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (20)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 363) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
82
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rz.sv
Executable file
82
wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rz.sv
Executable file
@ -0,0 +1,82 @@
|
||||
`timescale 1ns/1ps
|
||||
module tb ();
|
||||
|
||||
logic [63:0] op1;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
logic clk;
|
||||
logic [63:0] yexpected;
|
||||
logic [63:0] vectornum, errors; // bookkeeping variables
|
||||
logic [135:0] testvectors[50000:0]; // array of testvectors
|
||||
logic [7:0] flags_expected;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
// instantiate device under test
|
||||
fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("f64_sqrt_rz.out");
|
||||
$readmemh("f64_sqrt_rz.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
start = 1'b0;
|
||||
// reset
|
||||
reset = 1; #27; reset = 0;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#0 op_type = 1'b1;
|
||||
#0 P = 1'b0;
|
||||
#0 rm = 2'b01;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (~reset)
|
||||
begin
|
||||
#0; {op1, yexpected, flags_expected} = testvectors[vectornum];
|
||||
#50 start = 1'b1;
|
||||
repeat (2)
|
||||
@(posedge clk);
|
||||
// deassert start after 2 cycles
|
||||
start = 1'b0;
|
||||
repeat (20)
|
||||
@(posedge clk);
|
||||
$fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
|
||||
vectornum = vectornum + 1;
|
||||
end // if (~reset)
|
||||
if (vectornum == 363) begin
|
||||
$display("%d vectors processed", vectornum);
|
||||
$finish;
|
||||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
72
wally-pipelined/src/fpu/fpdivsqrt/test_divconvDP.sv
Executable file
72
wally-pipelined/src/fpu/fpdivsqrt/test_divconvDP.sv
Executable file
@ -0,0 +1,72 @@
|
||||
module tb;
|
||||
|
||||
logic [52:0] d, n;
|
||||
logic reset;
|
||||
|
||||
logic [63:0] q, qm, qp, rega_out, regb_out, regc_out;
|
||||
logic [127:0] regr_out;
|
||||
|
||||
logic start;
|
||||
logic error;
|
||||
logic op_type;
|
||||
|
||||
logic done;
|
||||
logic load_rega;
|
||||
logic load_regb;
|
||||
logic load_regc;
|
||||
logic load_regr;
|
||||
logic [1:0] sel_muxa;
|
||||
logic [1:0] sel_muxb;
|
||||
logic sel_muxr;
|
||||
|
||||
logic clk;
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
divconv dut (q, qm, qp, rega_out, regb_out, regc_out, regr_out,
|
||||
d, n, sel_muxa, sel_muxb, sel_muxr, reset, clk,
|
||||
load_rega, load_regb, load_regc, load_regr);
|
||||
fsm control (done, load_rega, load_regb, load_regc, load_regr,
|
||||
sel_muxa, sel_muxb, sel_muxr,
|
||||
clk, reset, start, error, op_type);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("divconvDP.out");
|
||||
#700 $finish;
|
||||
end
|
||||
|
||||
always
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#5 $fdisplay(desc3, "%b %b %b | %h %h | %h %h %h | %h %h %h %h", sel_muxa,
|
||||
sel_muxb, sel_muxr, d, n, q, qm, qp, rega_out, regb_out, regc_out, regr_out);
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
#0 start = 1'b0;
|
||||
#0 n = 53'h1C_0000_0000_0000; // 1.75
|
||||
#0 d = 53'h1E_0000_0000_0000; // 1.875
|
||||
#0 reset = 1'b1;
|
||||
|
||||
#20 reset = 1'b0;
|
||||
#20 start = 1'b1;
|
||||
#40 start = 1'b0;
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
184
wally-pipelined/src/fpu/fpdivsqrt/test_fpdiv.sv
Executable file
184
wally-pipelined/src/fpu/fpdivsqrt/test_fpdiv.sv
Executable file
@ -0,0 +1,184 @@
|
||||
`timescale 1ps/1ps
|
||||
module tb;
|
||||
|
||||
logic [63:0] op1;
|
||||
logic [63:0] op2;
|
||||
logic [1:0] rm;
|
||||
logic op_type;
|
||||
logic P;
|
||||
logic OvEn;
|
||||
logic UnEn;
|
||||
|
||||
logic start;
|
||||
logic reset;
|
||||
logic clk;
|
||||
|
||||
logic [63:0] AS_Result;
|
||||
logic [4:0] Flags;
|
||||
logic Denorm;
|
||||
logic done;
|
||||
|
||||
integer handle3;
|
||||
integer desc3;
|
||||
|
||||
fpdivP dut (done, AS_Result, Flags, Denorm, op1, op2,
|
||||
rm, op_type, P, OvEn, UnEn,
|
||||
start, reset, clk);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
forever #333 clk = ~clk;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("fpdiv.out");
|
||||
end
|
||||
|
||||
always
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#5 $fdisplay(desc3, "%h %h | %h %h %h",
|
||||
op1, op2, AS_Result, Flags, Denorm);
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
#0 start = 1'b0;
|
||||
#0 P = 1'b0;
|
||||
#0 OvEn = 1'b0;
|
||||
#0 UnEn = 1'b0;
|
||||
// 00 round-to-nearest-even
|
||||
// 01 round-toward-zero
|
||||
// 10 round-toward-plus infinity
|
||||
// 11 round-toward-minus infinity
|
||||
#0 rm = 2'b00;
|
||||
#0 op_type = 1'b1;
|
||||
|
||||
#0 op1 = 64'h3ffc_0000_0000_0000; // 1.75
|
||||
#0 op2 = 64'h3ffe_0000_0000_0000; // 1.875
|
||||
|
||||
// P=1 divide
|
||||
//#0 op1 = 64'h8683_F7FF_0000_0000;
|
||||
//#0 op2 = 64'hC07F_3FFF_0000_0000;
|
||||
|
||||
//#0 op1 = 64'h4F95_1295_0000_0000;
|
||||
//#0 op2 = 64'h4F95_1295_0000_0000;
|
||||
|
||||
//#0 op1 = 64'h4020_5fff_ffff_ffff;
|
||||
//#0 op2 = 64'hbcaf_ffff_ffff_ffff;
|
||||
|
||||
//#0 op1 = 64'h3fed_c505_fada_95fd; // 0.930300703
|
||||
//#0 op2 = 64'h3ffe_0000_0000_0000; // 12.9303733
|
||||
|
||||
//#0 op1 = 64'h3ffe_e219_652b_d3c3; // 1.9302
|
||||
//#0 op2 = 64'h3ff7_346d_c5d6_3886; // 1.4503
|
||||
//#0 op1 = 64'h404f_b1d4_9518_2a99; // 63.3893
|
||||
//#0 op2 = 64'h4020_9b94_d940_7896; // 8.30387
|
||||
//#0 op1 = 64'h3ff6_3d98_4781_6b47; // 1.390037803
|
||||
//#0 op2 = 64'h3fd7_b540_56e5_c87a; // 0.370437703
|
||||
//#0 op1 = 64'h3fed_c505_fada_95fd; // 0.930300703
|
||||
//#0 op2 = 64'h4029_dc59_e3a1_24a8; // 12.9303733
|
||||
//#0 op1 = 64'h41E0_0003_FFFB_FFFF;
|
||||
//#0 op2 = 64'hBFDF_FFFF_FFEF_FFFF;
|
||||
//#0 op1 = 64'h41E0_0003_FFFB_FFFF;
|
||||
//#0 op2 = 64'h3FDF_FFFF_FFEF_FFFF;
|
||||
//#0 op1 = 64'hB68F_FFF8_0000_00FF;
|
||||
//#0 op2 = 64'h3F90_8000_0007_FFFF;
|
||||
//#0 op1 = 64'h0000_0000_0000_0000;
|
||||
//#0 op2 = 64'hA57F_319E_DE38_F755;
|
||||
//#0 op1 = 64'hC1DF_FFFF_FFE0_0080;
|
||||
//#0 op2 = 64'h3FA4_8EDF_3623_F076;
|
||||
//#0 op1 = 64'hC030_00FF_FFFF_FFE0;
|
||||
//#0 op2 = 64'h47EF_FDFF_FDFF_FFFF;
|
||||
//#0 op1 = 64'h4030_00FF_FFFF_FFE0;
|
||||
//#0 op2 = 64'h47EF_FDFF_FDFF_FFFF;
|
||||
//#0 op1 = 64'h5555_5555_5555_5555; // 1.75
|
||||
//#0 op2 = 64'haaaa_aaaa_aaaa_aaaa; // 1.875
|
||||
//#0 op1 = 64'h3ffc_0000_0000_0000; // 1.75
|
||||
//#0 op2 = 64'h0000_0000_0000_0000; // 0.00 (Div0 exception)
|
||||
//#0 op1 = 64'h3ff7_10cb_0000_0000;
|
||||
//#0 op2 = 64'h3fb9_a36e_0000_0000;
|
||||
//#0 op1 = 64'h37e0_0000_0000_0001;
|
||||
//#0 op2 = 64'h3be6_a09e_667f_3bce;
|
||||
|
||||
//#0 op1 = 64'h37e0_0000_0000_0001;
|
||||
//#0 op1 = 64'h43d3_6fa3_cad3_f59e;
|
||||
//#0 op1 = 64'h2470_0000_ffff_ffef;
|
||||
//#0 op1 = 64'h7ff0_0000_0000_0000;
|
||||
//#0 op1 = 64'h7fef_ffff_ffff_ffff;
|
||||
//#0 op1 = 64'hffe0_0000_0000_0000;
|
||||
//#0 op2 = 64'h7fe0_0000_0000_0001;
|
||||
//#0 op1 = 64'h69ff_ff7f_0000_0000;
|
||||
//#0 op2 = 64'h0;
|
||||
//#0 op1 = 64'h3f7f_ffff_0000_0000;
|
||||
//#0 op1 = 64'h4180_0000_0000_0000;
|
||||
|
||||
|
||||
//#0 op1 = 64'h3fe0_0000_0000_0000; // 1.75 (SP)
|
||||
//#0 op2 = 64'h3ff0_0000_0000_0000; // 1.875 (SP)
|
||||
//#0 op1 = 64'h3ff7_10cb_0000_0000; // 1.75 (SP)
|
||||
//#0 op2 = 64'h3fb9_a36e_0000_0000; // 1.875 (SP)
|
||||
//#0 op1 = 64'h427d_8ea5_0000_0000; // 1.75 (SP)
|
||||
//#0 op2 = 64'h4104_dca7_0000_0000; // 1.875 (SP)
|
||||
//#0 op1 = 64'h3fb1_ecc2_0000_0000; // 1.75 (SP)
|
||||
//#0 op2 = 64'h3ebd_aa03_0000_0000; // 1.875 (SP)
|
||||
//#0 op1 = 64'h3f6e_2830_0000_0000;
|
||||
//#0 op2 = 64'h414e_e2cf_0000_0000;
|
||||
//#0 op1 = 64'h8683_f7ff_0000_0000;
|
||||
//#0 op2 = 64'hc07f_3fff_0000_0000;
|
||||
//#0 op1 = 64'h0100_0000_0000_0000;
|
||||
//#0 op2 = 64'h3400_00ef_0000_0000;
|
||||
//#0 op1 = 64'hbed5_6444_0000_0000;
|
||||
//#0 op2 = 64'h3e7f_f400_0000_0000;
|
||||
//#0 op1 = 64'h0100_087f_0000_0000;
|
||||
//#0 op2 = 64'hfe80_4fff_0000_0000;
|
||||
|
||||
|
||||
//#0 op1 = 64'hc513_492f_a359_69e3;
|
||||
//#0 op2 = 64'hbfcf_fdff_ffff_ffef;
|
||||
//#0 op1 = 64'h41E0_0003_FFFB_FFFF;
|
||||
//#0 op2 = 64'hBFDF_FFFF_FFEF_FFFF;
|
||||
//#0 op1 = 64'hf17ffffffff7fff0;
|
||||
//#0 op2 = 64'h001ffffffffffffe;
|
||||
//#0 op1 = 64'hC040_0000_0000_1000;
|
||||
//#0 op2 = 64'h802f_ff7f_ffff_ffc0;
|
||||
//#0 op1 = 64'h3800008000000002;
|
||||
//#0 op2 = 64'h7ff0000000000000;
|
||||
//#0 op1 = 64'h8020200007fffffe;
|
||||
//#0 op2 = 64'hc59000000000083f;
|
||||
//#0 op1 = 64'h0140008000fffffe;
|
||||
//#0 op2 = 64'hd2e0001ffffffffb;
|
||||
//#0 op1 = 64'h4013_95a7_515b_e3d9;
|
||||
//#0 op2 = 64'h8010_0000_0004_0007;
|
||||
//#0 op1 = 64'h0010_0000_0000_0000;
|
||||
//#0 op2 = 64'h3fff_ffff_ffff_ffff;
|
||||
//#0 op1 = 64'h0010_0000_0000_0000;
|
||||
//#0 op2 = 64'h4000_0000_0000_0001;
|
||||
//#0 op1 = 64'h4000000000000001;
|
||||
//#0 op2 = 64'h403000004007fffe; // _3fbfffff7ff00207_00000_0 | 3fbfffff7ff00206_0
|
||||
//#0 op1 = 64'hffe0_0000_0000_0000;
|
||||
//#0 op2 = 64'hc0a0_0000_4008_0000;
|
||||
//#0 op1 = 64'hffe0_0000_0000_0001;
|
||||
//#0 op2 = 64'hbfd0_0000_0000_0000;
|
||||
|
||||
//#0 op1 = 64'h801f_ffff_ffff_ffff;
|
||||
//#0 op2 = 64'h4000_0000_0000_0000;
|
||||
|
||||
|
||||
#0 reset = 1'b1;
|
||||
#1000 reset = 1'b0;
|
||||
#3000 start = 1'b1;
|
||||
#800 start = 1'b0;
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
endmodule // tb
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user