Merge branch 'main' into cache

wally-pipelined/src/muldiv/muldiv.sv

@@ -62,7 +62,7 @@ module muldiv (
 	 // Divide
 
 	// *** replace this clock gater
-	always @(posedge clk) begin
+	always @(negedge clk) begin
 	  enable_q <= ~StallM;
 	end
 	assign gclk = enable_q & clk;

wally-pipelined/testgen/privileged/testgen-IE.py

@@ -251,7 +251,7 @@ def writeVectors(a, xlen, storecmd):
 ##################################
 
 # change these to suite your tests
-tests = ["timerM", "timerS", "timerU", "softwareM", "softwareS", "softwareU"]
+tests = ["timerM"] #, "timerS", "timerU", "softwareM", "softwareS", "softwareU"]
 author = "ushakya@hmc.edu"
 xlens = [64, 32]
 numrand = 100;