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Retimed peripherals for AHB interface

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This commit is contained in:
David Harris 2021-02-26 00:55:41 -05:00
parent 4e6caf64d9
commit 24f767a404
8 changed files with 30 additions and 24 deletions
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2
wally-pipelined/src/fpu/build_temp/freg.sv
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@ -340,7 +340,7 @@ module freg3adr (
generate
for (i = 0; i < numRegs; i = i + 1) begin:register
floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
floprc #(`XLEN) reg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
end
endgenerate

2
wally-pipelined/src/fpu/fcsr.sv → wally-pipelined/src/fpu/dev/fcsr.sv
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@ -21,7 +21,7 @@ module fcsr(
//for clk-based write
assign regInput = (write) ? {24'h0,frm,flags} : regInput;
floprc #(32) (.clk(clk), .reset(reset), .clear(clear), .d(regInput), .q(regOutput));
floprc #(32) fcsrreg(.clk(clk), .reset(reset), .clear(clear), .d(regInput), .q(regOutput));
assign readData = regOutput;

0
wally-pipelined/src/fpu/fctrl.sv → wally-pipelined/src/fpu/dev/fctrl.sv
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0
wally-pipelined/src/fpu/fputop.sv → wally-pipelined/src/fpu/dev/fputop.sv
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6
wally-pipelined/src/fpu/freg.sv → wally-pipelined/src/fpu/dev/freg.sv
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@ -28,7 +28,7 @@ module freg1adr (
generate
for (i = 0; i < numRegs; i = i + 1) begin:register
floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
floprc #(`XLEN) freg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
end
endgenerate
@ -167,7 +167,7 @@ module freg2adr (
generate
for (i = 0; i < numRegs; i = i + 1) begin:register
floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
floprc #(`XLEN) freg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
end
endgenerate
@ -340,7 +340,7 @@ module freg3adr (
generate
for (i = 0; i < numRegs; i = i + 1) begin:register
floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
floprc #(`XLEN) freg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
end
endgenerate

8
wally-pipelined/src/uncore/clint.sv
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@ -44,7 +44,9 @@ module clint (
assign memread = MemRWclint[1];
assign memwrite = MemRWclint[0];
assign HRESPCLINT = 0; // OK
assign HREADYCLINT = 1; // Respond immediately
// assign HREADYCLINT = 1; // Respond immediately
always_ff @(posedge HCLK) // delay response
HREADYCLINT <= memread | memwrite;
// word aligned reads
generate
@ -63,7 +65,7 @@ module clint (
// register access
generate
if (`XLEN==64) begin
always_comb begin
always @(posedge HCLK) begin
case(entry)
16'h0000: HREADCLINT = {63'b0, MSIP};
16'h4000: HREADCLINT = MTIMECMP;
@ -85,7 +87,7 @@ module clint (
else MTIME <= MTIME + 1;
end
end else begin // 32-bit
always_comb begin
always @(posedge HCLK) begin
case(entry)
16'h0000: HREADCLINT = {31'b0, MSIP};
16'h4000: HREADCLINT = MTIMECMP[31:0];

28
wally-pipelined/src/uncore/gpio.sv
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@ -45,7 +45,9 @@ module gpio (
assign memread = MemRWgpio[1];
assign memwrite = MemRWgpio[0];
assign HRESPGPIO = 0; // OK
assign HREADYGPIO = 1; // Respond immediately
always_ff @(posedge HCLK) // delay response to data cycle
HREADYGPIO <= memread | memwrite;
// assign HREADYGPIO = 1; // Respond immediately
// word aligned reads
generate
@ -67,12 +69,12 @@ module gpio (
// register access
generate
if (`XLEN==64) begin
always_comb begin
always_ff @(posedge HCLK) begin
case(entry)
8'h00: HREADGPIO = {INPUT_EN, INPUT_VAL};
8'h08: HREADGPIO = {OUTPUT_VAL, OUTPUT_EN};
8'h40: HREADGPIO = 0; // OUT_XOR reads as 0
default: HREADGPIO = 0;
8'h00: HREADGPIO <= {INPUT_EN, INPUT_VAL};
8'h08: HREADGPIO <= {OUTPUT_VAL, OUTPUT_EN};
8'h40: HREADGPIO <= 0; // OUT_XOR reads as 0
default: HREADGPIO <= 0;
endcase
end
always_ff @(posedge HCLK or negedge HRESETn)
@ -86,14 +88,14 @@ module gpio (
if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ HWDATA[31:0]; // OUT_XOR
end
end else begin // 32-bit
always_comb begin
always_ff @(posedge HCLK) begin
case(entry)
8'h00: HREADGPIO = INPUT_VAL;
8'h04: HREADGPIO = INPUT_EN;
8'h08: HREADGPIO = OUTPUT_EN;
8'h0C: HREADGPIO = OUTPUT_VAL;
8'h40: HREADGPIO = 0; // OUT_XOR reads as 0
default: HREADGPIO = 0;
8'h00: HREADGPIO <= INPUT_VAL;
8'h04: HREADGPIO <= INPUT_EN;
8'h08: HREADGPIO <= OUTPUT_EN;
8'h0C: HREADGPIO <= OUTPUT_VAL;
8'h40: HREADGPIO <= 0; // OUT_XOR reads as 0
default: HREADGPIO <= 0;
endcase
end
always_ff @(posedge HCLK or negedge HRESETn)

8
wally-pipelined/src/uncore/uart.sv
View File

@ -48,11 +48,13 @@ module uart (
assign MEMWb = ~MemRWuart[0];
assign A = HADDR[2:0];
assign HRESPUART = 0; // OK
assign HREADYUART = 1; // Respond immediately
//assign HREADYUART = 1; // Respond immediately
always_ff @(posedge HCLK) // delay response to data cycle
HREADYUART <= ~MEMRb | ~MEMWb;
generate
if (`XLEN == 64) begin
always_comb begin
always @(posedge HCLK) begin
HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
case (HADDR)
3'b000: Din = HWDATA[7:0];
@ -66,7 +68,7 @@ module uart (
endcase
end
end else begin // 32-bit
always_comb begin
always @(posedge HCLK) begin
HREADUART = {Dout, Dout, Dout, Dout};
case (HADDR[1:0])
2'b00: Din = HWDATA[7:0];