forked from Github_Repos/cvw
Minor cosmetic elements on div.sv
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@ -130,7 +130,6 @@ module div (Qf, remf, done, divBusy, div0, N, D, clk, reset, start, S);
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// shifting N right by v+s so that (m+v+s) mod k = 0. And,
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// the quotient has to be aligned to the integer position.
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// Actual divider unit FIXME: r16 (jes)
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divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0,
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enable, otfzero, shiftResult);
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@ -159,11 +158,6 @@ module div (Qf, remf, done, divBusy, div0, N, D, clk, reset, start, S);
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// RISC-V has exceptions for divide by 0 and overflow (see Table 6.1 of spec)
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exception_int exc (QT, remT, N, S, div0, Max_N, D_NegOne, Qf, remf);
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// Delete me if works
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// RISC-V has exceptions for divide by 0 (Table 6.1 of SPEC)
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//mux2 #(64) exc1 (Q, {64{1'b1}}, div0, Qf);
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//mux2 #(64) exc2 (rem0, op1, div0, remf);
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endmodule // int32div
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module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0,
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