forked from Github_Repos/cvw
Steps to getting branch predictor benchmarks running.
This commit is contained in:
Ross Thompson
parent
9172e52286
commit
bff2d61a1f
testsBP
wally-pipelined
@ -45,7 +45,7 @@ _start:
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# set the stack pointer to the top of memory
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# 0x8000_0000 + 64K - 8 bytes
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li sp, 0x0000FFF8
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li sp, 0x007FFFF8
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jal ra, main
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jal ra, _halt
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@ -90,3 +90,4 @@ $(TARGET).memfile: $(TARGET)
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@echo 'Making memory file'
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exe2memfile0.pl $<
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extractFunctionRadix.sh $<.objdump
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cp $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/
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@ -3,4 +3,5 @@
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int fail();
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int simple_csrbr_test();
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int lbu_test();
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#endif
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@ -6,5 +6,6 @@ int main(){
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fail();
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return 0;
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}else
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res = lbu_test();
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return 0;
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}
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@ -18,7 +18,7 @@ my $maxaddress = 0;
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STDOUT->autoflush(1);
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# *** Ross Thompson I think there is a bug here needs to be +1
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print ("Processing $#ARGV memfiles: ");
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print ("Processing $#ARGV memfiles: \n");
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my $frac = $#ARGV/10;
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for(my $i=0; $i<=$#ARGV; $i++) {
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if ($i < 10 || $i % $frac == 0) { print ("$i ") };
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@ -40,7 +40,11 @@ for(my $i=0; $i<=$#ARGV; $i++) {
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if ($needsprocessing == 1) {
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open(FILE, $ofile) || die("Can't read $ofile");
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my $mode = 0; # parse for code
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my $section = "";
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my $data = "";
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my $address;
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my $first = 0;
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my $firstAddress;
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# initialize to all zeros;
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# *** need to fix the zeroing range. Not always 64K
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@ -49,57 +53,100 @@ for(my $i=0; $i<=$#ARGV; $i++) {
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}
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while(<FILE>) {
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# *** this mode stuff does not work if a section is missing or reordered.
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if ($mode == 0) { # Parse code
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# print("Examining $_\n");
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if (/^\s*(\S{1,16}):\s+(\S+)\s+/) {
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$address = &fixadr($1);
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my $instr = $2;
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my $len = length($instr);
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for (my $i=0; $i<$len/2; $i++) {
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$memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2);
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}
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# print ("address $address $instr\n");
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# objdump fill is divided into several .sections of which only some we want to actually process.
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# In general we want everything except the .comment and .*attributes
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if (/Disassembly of section (.*):/) {
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$section = $1;
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print ("setting section to $section\n");
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} else {
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# now check if the section is one we are interested in processing.
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#if ($section ne ".comment" && $section ne ".riscv.attributes" && $section =~ /\.debug.*/) {
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if ($section =~ "\.init|\.text|\..*data|\..*bss") {
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# the structure is: possible space(s) hex number: possible space(s) hex number space(s) junk
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# there are also lines we need to skip: possible space(s) hex number <string>:
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if (/^\s*([0-9A-Fa-f]{1,16}):\s+([0-9A-Fa-f]+).*$/) {
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$address = &fixadr($1);
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if ($first == 0) {
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$first = 1;
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$firstAddress = $address;
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}
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$data = $2;
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&emitData($address, $data);
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# my $len = length($data);
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# for (my $i=0; $i<$len/2; $i++) {
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# $memfilebytes[$address+$i] = substr($data, $len-2-2*$i, 2);
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# }
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# print ("Addr $address $data\n");
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# } elsif (/^\s*\.\.\./) {
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# print ("Got ...\n");
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# } else {
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# print ("No match\n");
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}
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}
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if (/Disassembly of section .data:/) { $mode = 1;}
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} elsif ($mode == 1) { # Parse data segment
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if (/^\s*(\S{1,16}):\s+(.*)/) {
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$address = &fixadr($1);
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# print "addresss $address maxaddress $maxaddress\n";
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if ($address > $maxaddress) { $maxaddress = $address; }
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my $line = $2;
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# merge chunks with spaces
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# *** might need to change
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$line =~ s/(\S)\s(\S)/$1$2/g;
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# strip off comments
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$line =~ /^(\S*)/;
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$payload = $1;
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&emitData($address, $payload);
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}
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if (/Disassembly of section .comment:/) { $mode = 2; }
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} elsif ($mode == 2) { # parse the comment section
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if (/Disassembly of section .riscv.attributes:/) { $mode = 3; }
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}
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}
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# # *** this mode stuff does not work if a section is missing or reordered.
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# if ($mode == 0) { # Parse code
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# # print("Examining $_\n");
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# if (/^\s*(\S{1,16}):\s+(\S+)\s+/) {
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# $address = &fixadr($1);
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# my $instr = $2;
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# my $len = length($instr);
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# for (my $i=0; $i<$len/2; $i++) {
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# $memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2);
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# }
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# print ("address $address $instr\n");
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# }
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# if (/Disassembly of section .data:/) { $mode = 1;}
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# } elsif ($mode == 1) { # Parse data segment
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# if (/^\s*(\S{1,16}):\s+(.*)/) {
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# $address = &fixadr($1);
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# # print "addresss $address maxaddress $maxaddress\n";
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# if ($address > $maxaddress) { $maxaddress = $address; }
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# my $line = $2;
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# # merge chunks with spaces
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# # *** might need to change
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# $line =~ s/(\S)\s(\S)/$1$2/g;
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# # strip off comments
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# $line =~ /^(\S*)/;
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# $payload = $1;
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# &emitData($address, $payload);
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# }
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# if (/Disassembly of section .comment:/) { $mode = 2; }
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# } elsif ($mode == 2) { # parse the comment section
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# if (/Disassembly of section .riscv.attributes:/) { $mode = 3; }
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# }
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}
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close(FILE);
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$maxaddress += 32; # pad some zeros at the end
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$maxaddress = $address + 32; # pad some zeros at the end
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# print to memory file
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# *** this is a problem
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if ($fname =~ /rv32/) {
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open(MEMFILE, ">$memfile") || die("Can't write $memfile");
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for (my $i=0; $i<= $maxaddress; $i = $i + 4) {
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for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 4) {
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for ($j=3; $j>=0; $j--) {
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print MEMFILE "$memfilebytes[$i+$j]";
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no warnings 'uninitialized';
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my $value = $memfilebytes[$i+$j];
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if ($value eq ""){
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print MEMFILE "00";
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} else {
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print MEMFILE "$memfilebytes[$i+$j]";
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}
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}
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print MEMFILE "\n";
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}
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close(MEMFILE);
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} else {
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open(MEMFILE, ">$memfile") || die("Can't write $memfile");
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for (my $i=0; $i<= $maxaddress; $i = $i + 8) {
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for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 8) {
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for ($j=7; $j>=0; $j--) {
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print MEMFILE "$memfilebytes[$i+$j]";
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no warnings 'uninitialized';
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my $value = $memfilebytes[$i+$j];
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if ($value eq ""){
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print MEMFILE "00";
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} else {
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print MEMFILE "$memfilebytes[$i+$j]";
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}
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}
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print MEMFILE "\n";
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}
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@ -141,5 +188,6 @@ sub fixadr {
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# strip off leading 8 from address and convert to decimal
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# if the leading 8 is not present don't remove.
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my $adr = shift;
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#print "addr $adr\n";
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return hex($adr);
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}
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@ -66,18 +66,18 @@
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIMBASE 32'h00080000
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`define BOOTTIMBASE 32'h00800000
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h00000000
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`define TIMRANGE 32'h0007FFFF
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`define CLINTBASE 32'h02000000
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`define CLINTRANGE 32'h0000FFFF
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`define GPIOBASE 32'h10012000
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`define GPIORANGE 32'h000000FF
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`define UARTBASE 32'h10000000
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`define UARTRANGE 32'h00000007
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`define PLICBASE 32'h0C000000
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`define PLICRANGE 32'h03FFFFFF
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`define TIMRANGE 32'h007FFFFF
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`define CLINTBASE 32'h02000000
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`define CLINTRANGE 32'h0000FFFF
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`define GPIOBASE 32'h10012000
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`define GPIORANGE 32'h000000FF
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`define UARTBASE 32'h10000000
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`define UARTRANGE 32'h00000007
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`define PLICBASE 32'h0C000000
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`define PLICRANGE 32'h03FFFFFF
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// Test modes
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@ -56,15 +56,14 @@ add wave -noupdate -group Bpred -expand -group direction -group other /testbench
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add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/DoForwardingF
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add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRD
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add wave -noupdate -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
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add wave -noupdate -group Bpred -group {bp wrong} -divider pcs
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCTargetE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
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add wave -noupdate -group Bpred -expand -group {bp wrong} -divider pcs
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCTargetE
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add wave -noupdate -group Bpred -expand -group BTB -divider Update
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
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@ -96,25 +95,25 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
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add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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@ -128,10 +127,11 @@ add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate /testbench/InstrFName
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add wave -noupdate -group dcache /testbench/dut/hart/MemAdrM
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add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
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add wave -noupdate -group dcache /testbench/dut/hart/WriteDataM
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add wave -noupdate -group dcache /testbench/dut/hart/dmem/MemRWM
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add wave -noupdate -expand -group dcache /testbench/dut/hart/MemAdrM
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add wave -noupdate -expand -group dcache -radix hexadecimal /testbench/dut/hart/MemPAdrM
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add wave -noupdate -expand -group dcache /testbench/dut/hart/WriteDataM
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add wave -noupdate -expand -group dcache /testbench/dut/hart/ReadDataW
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add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemRWM
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -150,15 +150,15 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALURe
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCW
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add wave -noupdate -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext0F
|
||||
add wave -noupdate -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext1F
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCW
|
||||
add wave -noupdate -expand -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNextF
|
||||
add wave -noupdate -expand -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext0F
|
||||
add wave -noupdate -expand -group PCS -group pcnextmux /testbench/dut/hart/ifu/PCNext1F
|
||||
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionAddr
|
||||
add wave -noupdate -group {function radix debug} -radix unsigned /testbench/FunctionName/FunctionName/ProgramAddrIndex
|
||||
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/reset
|
||||
@ -173,15 +173,53 @@ add wave -noupdate -group {function radix debug} /testbench/FunctionName/Functio
|
||||
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionAddr
|
||||
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/ProgramAddrIndex
|
||||
add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionName
|
||||
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTEN
|
||||
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
|
||||
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
|
||||
add wave -noupdate -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTEN
|
||||
add wave -noupdate -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
|
||||
add wave -noupdate -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
|
||||
add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultW
|
||||
add wave -noupdate /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||
add wave -noupdate /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||
add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/CSRCReadValM
|
||||
add wave -noupdate -radix unsigned /testbench/dut/imem/adrbits
|
||||
add wave -noupdate /testbench/dut/imem/rd
|
||||
add wave -noupdate /testbench/dut/imem/AdrF
|
||||
add wave -noupdate /testbench/dut/imem/InstrF
|
||||
add wave -noupdate /testbench/dut/InstrF
|
||||
add wave -noupdate /testbench/dut/InstrF
|
||||
add wave -noupdate -divider {New Divider}
|
||||
add wave -noupdate /testbench/dut/hart/ifu/InstrInF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/rd2
|
||||
add wave -noupdate /testbench/dut/hart/InstrRData
|
||||
add wave -noupdate /testbench/dut/hart/rd2
|
||||
add wave -noupdate /testbench/dut/hart/ebu/InstrRData
|
||||
add wave -noupdate /testbench/dut/hart/ebu/InstrPAdrF
|
||||
add wave -noupdate /testbench/dut/hart/ebu/HRDATA
|
||||
add wave -noupdate /testbench/dut/uncore/HSELUARTD
|
||||
add wave -noupdate /testbench/dut/uncore/HSELUART
|
||||
add wave -noupdate /testbench/dut/uncore/HSELTimD
|
||||
add wave -noupdate /testbench/dut/uncore/HSELTim
|
||||
add wave -noupdate /testbench/dut/uncore/HSELPLICD
|
||||
add wave -noupdate /testbench/dut/uncore/HSELPLIC
|
||||
add wave -noupdate /testbench/dut/uncore/HSELGPIOD
|
||||
add wave -noupdate /testbench/dut/uncore/HSELGPIO
|
||||
add wave -noupdate /testbench/dut/uncore/HSELCLINTD
|
||||
add wave -noupdate /testbench/dut/uncore/HSELCLINT
|
||||
add wave -noupdate /testbench/dut/uncore/HSELBootTimD
|
||||
add wave -noupdate /testbench/dut/uncore/HSELBootTim
|
||||
add wave -noupdate /testbench/dut/uncore/HREADTim
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim0
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/BASE
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/RANGE
|
||||
add wave -noupdate /testbench/memfilename
|
||||
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[770056]}
|
||||
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[771306]}
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HADDR
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/RAM
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim0
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 7} {13518 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 7} {15047768 ns} 0} {{Cursor 2} {34763538 ns} 0} {{Cursor 3} {15046271 ns} 0} {{Cursor 4} {15047307 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 229
|
||||
@ -197,4 +235,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {13489 ns} {13607 ns}
|
||||
WaveRestoreZoom {15047734 ns} {15047902 ns}
|
||||
|
||||
@ -317,6 +317,7 @@ string tests32i[] = {
|
||||
|
||||
string testsBP64[] = '{
|
||||
"rv64BP/simple", "10000",
|
||||
"rv64BP/qsort", "1000000",
|
||||
"rv64BP/sieve", "1000000"
|
||||
};
|
||||
string tests[];
|
||||
|
||||
Loading…
Reference in New Issue
Block a user