forked from Github_Repos/cvw
Forgot to add csr permission tests to testbench
This commit is contained in:
Domenico Ottolia
parent
682bc7b58e
commit
88ab07d456
@ -362,7 +362,9 @@ module testbench();
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"rv64p/WALLY-MVENDORID", "4000",
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"rv64p/WALLY-MIE", "3000",
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"rv64p/WALLY-MEDELEG", "4000",
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"rv64p/WALLY-IP", "2000"
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"rv64p/WALLY-IP", "2000",
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"rv64p/WALLY-CSR-PERMISSIONS-M", "5000",
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"rv64p/WALLY-CSR-PERMISSIONS-S", "3000"
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};
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string tests32p[] = '{
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@ -380,7 +382,9 @@ module testbench();
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"rv32p/WALLY-STVEC", "2000",
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"rv32p/WALLY-MIE", "3000",
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"rv32p/WALLY-MEDELEG", "4000",
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"rv32p/WALLY-IP", "3000"
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"rv32p/WALLY-IP", "3000",
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"rv32p/WALLY-CSR-PERMISSIONS-M", "5000",
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"rv32p/WALLY-CSR-PERMISSIONS-S", "3000"
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};
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string tests64periph[] = '{
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@ -428,8 +432,6 @@ module testbench();
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if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
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end
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//tests = {tests64a, tests};
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//tests = tests64p;
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end else begin // RV32
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// *** add the 32 bit bp tests
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if (TESTSPERIPH) begin
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@ -443,8 +445,6 @@ module testbench();
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if (`A_SUPPORTED) tests = {tests, tests32a};
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if (`MEM_VIRTMEM) tests = {tests, tests32mmu};
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end
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//tests = tests32p;
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end
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end
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248
wally-pipelined/testgen/privileged/testgen-CSR-PERMISSIONS.py
Normal file
248
wally-pipelined/testgen/privileged/testgen-CSR-PERMISSIONS.py
Normal file
@ -0,0 +1,248 @@
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#!/usr/bin/python3
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##################################
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# testgen-CSR-PERMISSIONS.py
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#
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# dottolia@hmc.edu 1 May 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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# Verify that an illegal instruction is raised when trying to write to csrs of a higher privilege
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#
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##################################
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# DOCUMENTATION:
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#
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# Most of the comments explaining what everything
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# does and the layout of the privileged tests
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# can be found in this file
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#
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###################################
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##################################
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# libraries
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##################################
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from datetime import datetime
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from random import randint
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from random import seed
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from random import getrandbits
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##################################
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# functions
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##################################
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testCount = 2
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def writeVectors(storecmd, testMode):
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global testnum
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csrs = ["status", "edeleg", "ideleg", "ie", "tvec", "counteren", "scratch", "epc", "cause", "tval", "ip"]
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if testMode == "s":
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csrs.append("atp")
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#csrs = ["status"]
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for csrStart in csrs:
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for i in range(0, testCount):
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a = 1
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csr = testMode + csrStart
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# only check for CSR changes if testing machine-mode registers
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csrWillChange = testMode == "s" or csrStart == "status" or csrStart == "epc" or csrStart == "cause" or csrStart == "tval"
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newCSRValue = "" if testMode == "s" else "csrr x24, " + csr
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f.write(f"""
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li x13, 1
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""")
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fromModeOptions = ["s", "u"] if testMode == "m" else ["u"]
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for fromMode in fromModeOptions:
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label = f"""{fromMode}_{csr}_{testnum}"""
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endlabel = f"""_j_end_{label}"""
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# This is all from testgen-TVAL.py, within the for loop on returningInstruction
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#
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# x25: mepc value
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# x24: new csr value
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# x23: original csr value
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lines = f"""
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li x30, 0
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la x1, _m_trap_from_{label}
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csrw mtvec, x1
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csrr x23, {csr}
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j _j_test_{label}
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_m_trap_from_{label}:
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bnez x30, {endlabel}
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csrr x25, mcause
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{newCSRValue}
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csrrs x20, mepc, x0
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addi x20, x20, 4
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csrrw x0, mepc, x20
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mret
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_j_test_{label}:
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"""
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lines += f"""
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li x1, 0b110000000000
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csrrc x0, mstatus, x1
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li x1, 0b0100000000000
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csrrs x0, mstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrw mepc, x1
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mret
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# We're now in supervisor mode...
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"""
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# Code to bring us down to user mode
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if fromMode == "u":
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lines += f"""
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li x1, 0b110000000000
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csrrc x0, sstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the sret instruction
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csrw sepc, x1
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sret
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# We're now in user mode...
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"""
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f.write(lines)
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writeTest(storecmd, f, r, f"""csrrw x1, {csr}, x0""", csrWillChange)
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writeTest(storecmd, f, r, f"""csrrw x0, {csr}, x13""", csrWillChange)
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writeTest(storecmd, f, r, f"""csrrwi x0, {csr}, {a}""", csrWillChange)
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if a != 0:
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writeTest(storecmd, f, r, f"""csrrs x0, {csr}, x13""", csrWillChange)
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writeTest(storecmd, f, r, f"""csrrc x0, {csr}, x13""", csrWillChange)
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writeTest(storecmd, f, r, f"""csrrsi x0, {csr}, {a}""", csrWillChange)
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writeTest(storecmd, f, r, f"""csrrci x0, {csr}, {a}""", csrWillChange)
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f.write(f"""
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li x30, 1
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ebreak
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{endlabel}:
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""")
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def writeTest(storecmd, f, r, test, csrWillChange):
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global testnum
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test = f"""
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_jdo{testnum}:
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li x25, 0xDEADBEA7
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{test}
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{storecmd} x25, 0(x7)
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addi x7, x7, {wordsize}
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"""
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# We expect x25 to always be an illegal instruction
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expected = 2
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f.write(test)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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if not csrWillChange:
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# We expect x24 should be equal to x23
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expected = 0
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f.write(f"""
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sub x25, x24, x23
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{storecmd} x25, 0(x7)
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addi x7, x7, {wordsize}
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""")
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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##################################
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# main body
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##################################
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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# setup
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# Change this seed to a different constant value for every test
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seed(0xC363DAEB9193AB45) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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if (xlen == 32):
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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for testMode in ["m", "s"]:
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-CSR-PERMISSIONS-" + testMode.upper()
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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storeAddressOffset = 0
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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f.write(f"""
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add x7, x6, x0
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csrr x19, mtvec
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""")
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writeVectors(storecmd, testMode)
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f.write(f"""
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csrw mtvec, x19
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""")
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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@ -43,6 +43,8 @@ def writeVectors(storecmd):
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# Supervisor Software Interrupt: True, 1
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# Machine Software Interrupt: True, 2
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writeTest(storecmd, f, r, "timer-interrupt", True, -1) # code determined inside of writeTest
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# User external input: True, 8
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# Supervisor external input: True, 9
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# Machine externa input: True, 11
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@ -92,13 +94,85 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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global testMode
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global isInterrupts
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beforeTest = ""
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if interrupt != isInterrupts:
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return
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isTimerInterruptTest = test == "timer-interrupt"
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delegateType = "i" if interrupt else "e"
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for mode in (["m", "s", "u"] if testMode == "m" else ["s", "u"]):
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if isTimerInterruptTest:
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clintAddr = "0x2004000"
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if test == "ecall":
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if mode == "m":
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code = 7
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test = f"""
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la x18, {clintAddr}
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{storecmd} x0, 0(x18)
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"""
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elif mode == "s":
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code = 5
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test = ""
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else:
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code = 4
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test = ""
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ieMask = 1 << code
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statusMask = 0b1010
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beforeTest = f"""
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li x1, {statusMask}
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csrrs x0, mstatus, x1
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li x1, 0b0010
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csrrs x0, sstatus, x1
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la x18, {clintAddr}
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lw x11, 0(x18)
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li x1, 0x7fffffffffffffff
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{storecmd} x1, 0(x18)
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li x1, {ieMask}
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csrrs x0, mie, x1
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li x1, {ieMask}
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csrrs x0, sie, x1
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"""
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resetHander = f"""
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#li x1, 0x80
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#csrrc x0, sie, x1
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li x1, {ieMask}
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csrrc x0, mie, x1
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li x1, {ieMask}
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csrrc x0, sie, x1
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li x1, {statusMask}
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csrrc x0, mstatus, x1
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li x1, 0b0010
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csrrc x0, sstatus, x1
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la x18, {clintAddr}
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{storecmd} x11, 0(x18)
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"""
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if mode == "s":
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beforeTest += f"""
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li x1, {ieMask}
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csrrs x0, sip, x1
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"""
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resetHander += f"""
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li x1, {ieMask}
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csrrc x0, sip, x1
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"""
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elif test == "ecall":
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if mode == "m":
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code = 11
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elif mode == "s":
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@ -121,6 +195,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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j _j_test_{labelSuffix}
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_j_m_trap_{labelSuffix}:
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{resetHander}
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li x25, 3
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csrr x1, mepc
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@ -130,6 +205,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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mret
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_j_s_trap_{labelSuffix}:
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{resetHander}
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li x25, 1
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csrr x1, sepc
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@ -150,11 +226,12 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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csrw m{delegateType}deleg, x1
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"""
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lines = original + "\n" + test
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if mode != "m":
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lines = f"""
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{original}
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{beforeTest}
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li x1, 0b110000000000
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csrrc x28, {testMode}status, x1
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li x1, 0b{"01" if mode == "s" else "00"}00000000000
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@ -176,6 +253,11 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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""")
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else:
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lines = f"""
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{original}
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{beforeTest}
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{test}
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"""
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writeTestInner(storecmd, f, r, lines, 3)
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f.write(f"""
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