Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

This commit is contained in:
Domenico Ottolia 2021-04-15 16:57:27 -04:00
commit eb9e1843fc
3 changed files with 28 additions and 29 deletions

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@ -131,6 +131,7 @@ module ahblite (
else NextBusState = IDLE; // if (InstrReadF still high)
INSTRREADC: if (~HREADY) NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage.
else NextBusState = IDLE;
default: NextBusState = IDLE;
endcase
// stall signals

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@ -74,14 +74,13 @@ module ifu (
logic CompressedF;
logic [31:0] InstrRawD, InstrE, InstrW;
logic [31:0] nop = 32'h00000013; // instruction for NOP
logic [`XLEN-1:0] ITLBInstrPAdrF, ICacheInstrPAdrF;
// *** send this to the trap unit
logic ITLBPageFaultF;
tlb #(3) itlb(.TLBAccess(1'b1), .VirtualAddress(PCF),
.PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),
.TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
.PhysicalAddress(ITLBInstrPAdrF), .TLBMiss(ITLBMissF),
.PhysicalAddress(PCPF), .TLBMiss(ITLBMissF),
.TLBHit(ITLBHitF), .TLBPageFault(ITLBPageFaultF),
.*);
@ -97,15 +96,11 @@ module ifu (
// assign InstrReadF = 1; // *** & ICacheMissF; add later
// jarred 2021-03-14 Add instrution cache block to remove rd2
assign PCPF = PCF; // Temporary workaround until iTLB is live
icache ic(
.*,
.InstrPAdrF(ICacheInstrPAdrF),
.UpperPCPF(PCPF[`XLEN-1:12]),
.LowerPCF(PCF[11:0])
);
// Prioritize the iTLB for reads if it wants one
mux2 #(`XLEN) instrPAdrMux(ICacheInstrPAdrF, ITLBInstrPAdrF, ITLBMissF, InstrPAdrF);
assign PrivilegedChangePCM = RetM | TrapM;

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@ -30,34 +30,37 @@
// Teo Ene 04/15:
// Temporarily removed paramterized priority encoder for non-parameterized one
// To get synthesis working quickly
// *** We should look for a better parameterized priority encoder. This has a
// bad code smell and might not synthesize
//module priority_encoder #(parameter BINARY_BITS = 3) (
// input [(2**BINARY_BITS)-1:0] one_hot,
// output [BINARY_BITS-1:0] binary
//);
//
// localparam ONE_HOT_BITS = 2**BINARY_BITS;
//
// genvar i, j;
// generate
// for (i = 0; i < ONE_HOT_BITS; i++) begin
// for (j = 0; j < BINARY_BITS; j++) begin
// if (i[j]) begin
// assign binary[j] = one_hot[i];
// end
// end
// end
// endgenerate
//
//endmodule
module priority_encoder #(parameter BINARY_BITS = 3) (
input logic [7:0] one_hot,
output logic [2:0] binary
);
// localparam ONE_HOT_BITS = 2**BINARY_BITS;
/*
genvar i, j;
generate
for (i = 0; i < ONE_HOT_BITS; i++) begin
for (j = 0; j < BINARY_BITS; j++) begin
if (i[j]) begin
assign binary[j] = one_hot[i];
end
end
end
endgenerate
*/
/*
logic [BINARY_BITS-1:0] binary_comb;
always_comb begin
binary_comb = 0;
for (int i = 0; i < ONE_HOT_BITS; i++)
if (one_hot[i]) binary_comb = i;
end
assign binary = binary_comb;
*/
always_comb
case (one_hot)
8'h1: binary=3'h0;