forked from Github_Repos/cvw
Added fp test to testbench
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@ -40,6 +40,11 @@ module testbench();
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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//logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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string tests64f[] = '{
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"rv64f/I-FADD-S-01", "2000",
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"rv64f/I-FCLASS-S-01", "2000"
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};
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string tests64a[] = '{
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"rv64a/WALLY-AMO", "2110",
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"rv64a/WALLY-LRSC", "2110"
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@ -337,14 +342,16 @@ string tests32i[] = {
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// pick tests based on modes supported
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initial
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if (`XLEN == 64) begin // RV64
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if(TESTSBP) begin
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tests = testsBP64;
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if (TESTSBP) begin
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tests = testsBP64;
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end else begin
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tests = {tests64i};
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if (`C_SUPPORTED) tests = {tests, tests64ic};
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else tests = {tests, tests64iNOc};
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if (`M_SUPPORTED) tests = {tests, tests64m};
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if (`A_SUPPORTED) tests = {tests, tests64a};
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tests = {tests64i};
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if (`C_SUPPORTED) tests = {tests, tests64ic};
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else tests = {tests, tests64iNOc};
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if (`M_SUPPORTED) tests = {tests, tests64m};
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if (`F_SUPPORTED) tests = {tests64f, tests};
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if (`D_SUPPORTED) tests = {tests64d, tests};
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if (`A_SUPPORTED) tests = {tests, tests64a};
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end
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// tests = {tests64a, tests};
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end else begin // RV32
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@ -353,6 +360,7 @@ string tests32i[] = {
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if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
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else tests = {tests, tests32iNOc};
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if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
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if (`F_SUPPORTED) tests = {tests32f, tests};
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if (`A_SUPPORTED) tests = {tests, tests32a};
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end
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string signame, memfilename;
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