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Reversed [0:...] with [...:0] in bus widths across the project

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This commit is contained in:
David Harris 2021-06-21 01:17:08 -04:00
parent d2ec04564b
commit 1ec90a5e1f
15 changed files with 20 additions and 20 deletions
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2
wally-pipelined/src/dmem/dmem.sv
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@ -71,7 +71,7 @@ module dmem (
input logic HWRITE,
input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage.
input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], // *** this one especially has a large note attached to it in pmpchecker.
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker.
output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.

2
wally-pipelined/src/generic/lzd.sv
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@ -81,7 +81,7 @@ module lzd4 (ZP, ZV, B);
lzd2 l1(ZPa, ZVa, B[1:0]);
lzd2 l2(ZPb, ZVb, B[3:2]);
assign ZP[0:0] = ZVb ? ZPb : ZPa;
assign ZP[0] = ZVb ? ZPb : ZPa;
assign ZP[1] = ~ZVb;
assign ZV = ZVa | ZVb;

2
wally-pipelined/src/ifu/ifu.sv
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@ -80,7 +80,7 @@ module ifu (
input logic HWRITE,
input logic ExecuteAccessF, //read, write, and atomic access are all set to zero because this mmu is onlt working with instructinos in the F stage.
input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so they're gonna have to come over into ifu and dmem
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
output logic PMPInstrAccessFaultF, PMAInstrAccessFaultF,
output logic ISquashBusAccessF,

2
wally-pipelined/src/mmu/mmu.sv
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@ -70,7 +70,7 @@ module mmu #(parameter ENTRY_BITS = 3,
input logic HWRITE,
input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
output logic SquashBusAccess, // *** send to privileged unit
output logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM,

4
wally-pipelined/src/mmu/pmpchecker.sv
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@ -48,7 +48,7 @@ module pmpchecker (
// boundary. It would be better to store the PMP address registers in a module
// somewhere in the CSR hierarchy and do PMP checking _within_ that module, so
// we don't have to pass around 16 whole registers.
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
input logic ExecuteAccessF, WriteAccessM, ReadAccessM,
@ -64,7 +64,7 @@ module pmpchecker (
logic [3:0] MatchedRegion;
logic Match, EnforcePMP;
logic [7:0] PMPCFG [0:15];
logic [7:0] PMPCFG [15:0];
// Bit i is high when the address is greater than or equal to PMPADR[i]
// Used for determining whether TOR PMP regions match

2
wally-pipelined/src/mmu/tlbcam.sv
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@ -47,7 +47,7 @@ module tlbcam #(parameter ENTRY_BITS = 3,
localparam NENTRIES = 2**ENTRY_BITS;
logic [1:0] PageTypeList [0:NENTRIES-1];
logic [1:0] PageTypeList [NENTRIES-1:0];
logic [NENTRIES-1:0] Matches;
// Create NENTRIES CAM lines, each of which will independently consider

2
wally-pipelined/src/mmu/tlbram.sv
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@ -41,7 +41,7 @@ module tlbram #(parameter ENTRY_BITS = 3) (
localparam NENTRIES = 2**ENTRY_BITS;
logic [`XLEN-1:0] ram [0:NENTRIES-1];
logic [`XLEN-1:0] ram [NENTRIES-1:0];
logic [`XLEN-1:0] PageTableEntry;
// Generate a flop for every entry in the RAM

2
wally-pipelined/src/privileged/csr.sv
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@ -61,7 +61,7 @@ module csr #(parameter
output logic STATUS_MXR, STATUS_SUM,
output logic STATUS_MPRV,
output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW,
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,

4
wally-pipelined/src/privileged/csrm.sv
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@ -91,7 +91,7 @@ module csrm #(parameter
output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
// 64-bit registers in RV64, or two 32-bit registers in RV32
output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW,
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
input logic [11:0] MIP_REGW, MIE_REGW,
output logic WriteMSTATUSM,
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
@ -104,7 +104,7 @@ module csrm #(parameter
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
logic WritePMPCFG0M, WritePMPCFG2M;
logic WritePMPADDRM [0:15];
logic WritePMPADDRM [15:0];
localparam MISA_26 = (`MISA) & 32'h03ffffff;

2
wally-pipelined/src/privileged/privileged.sv
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@ -69,7 +69,7 @@ module privileged (
output logic [`XLEN-1:0] SATP_REGW,
output logic STATUS_MXR, STATUS_SUM,
output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW,
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
output logic [2:0] FRM_REGW
);

2
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -121,7 +121,7 @@ module wallypipelinedhart (
logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
logic DSquashBusAccessM, ISquashBusAccessF;
logic [5:0] DHSELRegionsM, IHSELRegionsF;
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1];
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // signals being sent from privileged unit to pmp/pma in dmem and ifu.
assign HSELRegions = ExecuteAccessF ? IHSELRegionsF : DHSELRegionsM; // *** this is a pure guess on how one of these should be selected. it passes tests, but is it the right way to do this?

4
wally-pipelined/testbench/testbench-coremark.sv
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@ -28,8 +28,8 @@ module testbench();
logic clk;
logic reset;
int test, i, errors, totalerrors;
logic [31:0] sig32[0:10000];
logic [`XLEN-1:0] signature[0:10000];
logic [31:0] sig32[10000:0];
logic [`XLEN-1:0] signature[10000:0];
logic [`XLEN-1:0] testadr;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [`XLEN-1:0] meminit;

4
wally-pipelined/testbench/testbench-coremark_bare.sv
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@ -28,8 +28,8 @@ module testbench();
logic clk;
logic reset;
int test, i, errors, totalerrors;
logic [31:0] sig32[0:10000];
logic [`XLEN-1:0] signature[0:10000];
logic [31:0] sig32[10000:0];
logic [`XLEN-1:0] signature[10000:0];
logic [`XLEN-1:0] testadr;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [`XLEN-1:0] meminit;

2
wally-pipelined/testbench/testbench-linux.sv
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@ -70,7 +70,7 @@ module testbench();
logic SvMode, PTE_R, PTE_X;
logic [`XLEN-1:0] SATP, PTE;
logic [55:0] BaseAdr, PAdr;
logic [8:0] VPN [0:2];
logic [8:0] VPN [2:0];
logic [11:0] Offset;
int i;

4
wally-pipelined/testbench/testbench-privileged.sv
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@ -34,8 +34,8 @@ module testbench();
logic reset;
int test, i, errors, totalerrors;
logic [31:0] sig32[0:10000];
logic [`XLEN-1:0] signature[0:10000];
logic [31:0] sig32[10000:0];
logic [`XLEN-1:0] signature[10000:0];
logic [`XLEN-1:0] testadr;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
//logic [31:0] InstrW;