forked from Github_Repos/cvw
relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.
This commit is contained in:
Ross Thompson
parent
9f16d08d0d
commit
5b70eb86b0
@ -7,19 +7,19 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -expand -group alu -divider internals
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -243,7 +243,6 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DisableTranslation
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemRWM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DataStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW
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@ -294,42 +293,7 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUTranslate
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add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/pagetablewalker/WalkerState
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add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/pagetablewalker/HPTWStall
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/HPTWRead
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/EndWalk
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add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/MMUReadPTE
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add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/PRegEn
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add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/CurrentPTE
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add wave -noupdate -expand -group ptwalker -divider data
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/TranslationPAdr
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/ValidPTE
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/LeafPTE
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/TranslationPAdr
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageTableEntry
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageType
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/ITLBWriteF
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/DTLBWriteM
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerInstrPageFaultF
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerLoadPageFaultM
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerStorePageFaultM
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/MMUStall
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/EndWalk
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr
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add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState
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add wave -noupdate -expand -group {LSU ARB} -color {Medium Orchid} /testbench/dut/hart/arbiter/SelPTW
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/pagetablewalker/MMUStall
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWTranslate
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWRead
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWPAdr
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReadPTE
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReady
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add wave -noupdate -expand -group {LSU ARB} -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
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add wave -noupdate /testbench/dut/hart/lsu/DataStall
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add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
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@ -356,7 +320,6 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
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add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
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add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate /testbench/dut/hart/pagetablewalker/StartWalk
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add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/DisableTranslation
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add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/VirtualAddress
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add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/CAMHit
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@ -367,8 +330,8 @@ add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/TLBWr
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add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/PTEWriteVal
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add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/WriteLines
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 8} {4545 ns} 0} {{Cursor 3} {3377 ns} 0} {{Cursor 4} {3215 ns} 0}
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quietly wave cursor active 1
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WaveRestoreCursors {{Cursor 8} {4545 ns} 0} {{Cursor 3} {2540 ns} 0} {{Cursor 4} {681 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 189
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configure wave -justifyvalue left
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@ -383,4 +346,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {4209 ns} {4657 ns}
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WaveRestoreZoom {2313 ns} {2789 ns}
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@ -31,8 +31,7 @@
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic DataStall,
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output logic HPTWReady,
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output logic DCacheStall,
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// Memory Stage
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// connected to cpu (controls)
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@ -72,15 +71,17 @@ module lsu (
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// mmu management
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// page table walker
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input logic [`XLEN-1:0] PageTableEntryM,
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input logic [1:0] PageTypeM,
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, // from csr
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input logic DTLBWriteM,
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output logic DTLBMissM,
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input logic DisableTranslation, // used to stop intermediate PTE physical addresses being saved to TLB.
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input logic [`XLEN-1:0] PCF,
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input logic ITLBMissF,
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output logic [`XLEN-1:0] PageTableEntryF,
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output logic [1:0] PageTypeF,
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output logic ITLBWriteF,
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output logic WalkerInstrPageFaultF,
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output logic WalkerLoadPageFaultM,
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output logic WalkerStorePageFaultM,
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output logic DTLBHitM, // not connected
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@ -119,14 +120,106 @@ module lsu (
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logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem
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// *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
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logic DTLBMissM;
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logic [`XLEN-1:0] PageTableEntryM;
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logic [1:0] PageTypeM;
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logic DTLBWriteM;
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logic [`XLEN-1:0] MMUReadPTE;
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logic MMUReady;
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logic HPTWStall;
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logic [`XLEN-1:0] MMUPAdr;
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logic MMUTranslate;
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logic HPTWRead;
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logic [1:0] MemRWMtoLSU;
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logic [2:0] Funct3MtoLSU;
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logic [1:0] AtomicMtoLSU;
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logic [`XLEN-1:0] MemAdrMtoLSU;
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logic [`XLEN-1:0] WriteDataMtoLSU;
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logic [`XLEN-1:0] ReadDataWFromLSU;
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logic StallWtoLSU;
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logic CommittedMfromLSU;
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logic SquashSCWfromLSU;
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logic DataMisalignedMfromLSU;
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logic HPTWReady;
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logic LSUStall;
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logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB.
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// for time being until we have a dcache the AHB Lite read bus HRDATAW will be connected to the
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// CPU's read data input ReadDataW.
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assign ReadDataW = HRDATAW;
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assign ReadDataWFromLSU = HRDATAW;
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pagetablewalker pagetablewalker(
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.clk(clk),
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.reset(reset),
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.SATP_REGW(SATP_REGW),
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.PCF(PCF),
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.MemAdrM(MemAdrM),
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.ITLBMissF(ITLBMissF),
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.DTLBMissM(DTLBMissM),
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.MemRWM(MemRWM),
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.PageTableEntryF(PageTableEntryF),
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.PageTableEntryM(PageTableEntryM),
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.PageTypeF(PageTypeF),
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.PageTypeM(PageTypeM),
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.ITLBWriteF(ITLBWriteF),
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.DTLBWriteM(DTLBWriteM),
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.MMUReadPTE(MMUReadPTE),
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.MMUReady(HPTWReady),
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.HPTWStall(HPTWStall),
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.MMUPAdr(MMUPAdr),
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.MMUTranslate(MMUTranslate),
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.HPTWRead(HPTWRead),
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.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
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.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
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.WalkerStorePageFaultM(WalkerStorePageFaultM));
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// arbiter between IEU and pagetablewalker
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lsuArb arbiter(.clk(clk),
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.reset(reset),
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// HPTW connection
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.HPTWTranslate(MMUTranslate),
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.HPTWRead(HPTWRead),
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.HPTWPAdr(MMUPAdr),
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.HPTWReadPTE(MMUReadPTE),
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.HPTWStall(HPTWStall),
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// CPU connection
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.MemRWM(MemRWM),
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.Funct3M(Funct3M),
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.AtomicM(AtomicM),
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.MemAdrM(MemAdrM),
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.WriteDataM(WriteDataM), // *** Need to remove this.
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.StallW(StallW),
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.ReadDataW(ReadDataW),
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.CommittedM(CommittedM),
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.SquashSCW(SquashSCW),
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.DataMisalignedM(DataMisalignedM),
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.DCacheStall(DCacheStall),
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// LSU
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.DisableTranslation(DisableTranslation),
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.MemRWMtoLSU(MemRWMtoLSU),
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.Funct3MtoLSU(Funct3MtoLSU),
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.AtomicMtoLSU(AtomicMtoLSU),
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.MemAdrMtoLSU(MemAdrMtoLSU),
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.WriteDataMtoLSU(WriteDataMtoLSU), // *** ??????????????
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.StallWtoLSU(StallWtoLSU),
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.CommittedMfromLSU(CommittedMfromLSU),
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.SquashSCWfromLSU(SquashSCWfromLSU),
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.DataMisalignedMfromLSU(DataMisalignedMfromLSU),
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.ReadDataWFromLSU(ReadDataWFromLSU),
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.DataStall(LSUStall));
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mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0))
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dmmu(.TLBAccessType(MemRWM),
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.VirtualAddress(MemAdrM),
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.Size(Funct3M[1:0]),
|
||||
dmmu(.TLBAccessType(MemRWMtoLSU),
|
||||
.VirtualAddress(MemAdrMtoLSU),
|
||||
.Size(Funct3MtoLSU[1:0]),
|
||||
.PTEWriteVal(PageTableEntryM),
|
||||
.PageTypeWriteVal(PageTypeM),
|
||||
.TLBWrite(DTLBWriteM),
|
||||
@ -137,45 +230,46 @@ module lsu (
|
||||
.TLBPageFault(DTLBPageFaultM),
|
||||
.ExecuteAccessF(1'b0),
|
||||
.AtomicAccessM(AtomicMaskedM[1]),
|
||||
.WriteAccessM(MemRWM[0]),
|
||||
.ReadAccessM(MemRWM[1]),
|
||||
.WriteAccessM(MemRWMtoLSU[0]),
|
||||
.ReadAccessM(MemRWMtoLSU[1]),
|
||||
.SquashBusAccess(DSquashBusAccessM),
|
||||
.DisableTranslation(DisableTranslation),
|
||||
// .SelRegions(DHSELRegionsM),
|
||||
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
|
||||
|
||||
// Specify which type of page fault is occurring
|
||||
assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWM[1];
|
||||
assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWM[0];
|
||||
assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLSU[1];
|
||||
assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLSU[0];
|
||||
|
||||
// Determine if an Unaligned access is taking place
|
||||
always_comb
|
||||
case(Funct3M[1:0])
|
||||
2'b00: DataMisalignedM = 0; // lb, sb, lbu
|
||||
2'b01: DataMisalignedM = MemAdrM[0]; // lh, sh, lhu
|
||||
2'b10: DataMisalignedM = MemAdrM[1] | MemAdrM[0]; // lw, sw, flw, fsw, lwu
|
||||
2'b11: DataMisalignedM = |MemAdrM[2:0]; // ld, sd, fld, fsd
|
||||
case(Funct3MtoLSU[1:0])
|
||||
2'b00: DataMisalignedMfromLSU = 0; // lb, sb, lbu
|
||||
2'b01: DataMisalignedMfromLSU = MemAdrMtoLSU[0]; // lh, sh, lhu
|
||||
2'b10: DataMisalignedMfromLSU = MemAdrMtoLSU[1] | MemAdrMtoLSU[0]; // lw, sw, flw, fsw, lwu
|
||||
2'b11: DataMisalignedMfromLSU = |MemAdrMtoLSU[2:0]; // ld, sd, fld, fsd
|
||||
endcase
|
||||
|
||||
// Squash unaligned data accesses and failed store conditionals
|
||||
// *** this is also the place to squash if the cache is hit
|
||||
// Changed DataMisalignedM to a larger combination of trap sources
|
||||
// Changed DataMisalignedMfromLSU to a larger combination of trap sources
|
||||
// NonBusTrapM is anything that the bus doesn't contribute to producing
|
||||
// By contrast, using TrapM results in circular logic errors
|
||||
assign MemReadM = MemRWM[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
|
||||
assign MemWriteM = MemRWM[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED;
|
||||
assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ;
|
||||
assign MemReadM = MemRWMtoLSU[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
|
||||
assign MemWriteM = MemRWMtoLSU[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED;
|
||||
assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoLSU : 2'b00 ;
|
||||
assign MemAccessM = MemReadM | MemWriteM;
|
||||
|
||||
// Determine if M stage committed
|
||||
// Reset whenever unstalled. Set when access successfully occurs
|
||||
flopr #(1) committedMreg(clk,reset,(CommittedM | CommitM) & StallM,preCommittedM);
|
||||
assign CommittedM = preCommittedM | CommitM;
|
||||
flopr #(1) committedMreg(clk,reset,(CommittedMfromLSU | CommitM) & StallM,preCommittedM);
|
||||
assign CommittedMfromLSU = preCommittedM | CommitM;
|
||||
|
||||
// Determine if address is valid
|
||||
assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
|
||||
assign LoadAccessFaultM = MemRWM[1];
|
||||
assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
|
||||
assign StoreAccessFaultM = MemRWM[0];
|
||||
assign LoadMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[1];
|
||||
assign LoadAccessFaultM = MemRWMtoLSU[1];
|
||||
assign StoreMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[0];
|
||||
assign StoreAccessFaultM = MemRWMtoLSU[0];
|
||||
|
||||
// Handle atomic load reserved / store conditional
|
||||
generate
|
||||
@ -184,9 +278,9 @@ module lsu (
|
||||
logic ReservationValidM, ReservationValidW;
|
||||
logic lrM, scM, WriteAdrMatchM;
|
||||
|
||||
assign lrM = MemReadM && AtomicM[0];
|
||||
assign scM = MemRWM[0] && AtomicM[0];
|
||||
assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
|
||||
assign lrM = MemReadM && AtomicMtoLSU[0];
|
||||
assign scM = MemRWMtoLSU[0] && AtomicMtoLSU[0];
|
||||
assign WriteAdrMatchM = MemRWMtoLSU[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
|
||||
assign SquashSCM = scM && ~WriteAdrMatchM;
|
||||
always_comb begin // ReservationValidM (next value of valid reservation)
|
||||
if (lrM) ReservationValidM = 1; // set valid on load reserve
|
||||
@ -195,15 +289,15 @@ module lsu (
|
||||
end
|
||||
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
|
||||
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
|
||||
flopenrc #(1) squashreg(clk, reset, FlushW, ~StallW, SquashSCM, SquashSCW);
|
||||
flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoLSU, SquashSCM, SquashSCWfromLSU);
|
||||
end else begin // Atomic operations not supported
|
||||
assign SquashSCM = 0;
|
||||
assign SquashSCW = 0;
|
||||
assign SquashSCWfromLSU = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Data stall
|
||||
//assign DataStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2);
|
||||
//assign LSUStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2);
|
||||
assign HPTWReady = (CurrState == STATE_READY);
|
||||
|
||||
|
||||
@ -224,22 +318,22 @@ module lsu (
|
||||
STATE_READY:
|
||||
if (DTLBMissM) begin
|
||||
NextState = STATE_PTW_READY;
|
||||
DataStall = 1'b1;
|
||||
LSUStall = 1'b1;
|
||||
end else if (AtomicMaskedM[1]) begin
|
||||
NextState = STATE_FETCH_AMO_1; // *** should be some misalign check
|
||||
DataStall = 1'b1;
|
||||
end else if((MemReadM & AtomicM[0]) | (MemWriteM & AtomicM[0])) begin
|
||||
LSUStall = 1'b1;
|
||||
end else if((MemReadM & AtomicMtoLSU[0]) | (MemWriteM & AtomicMtoLSU[0])) begin
|
||||
NextState = STATE_FETCH_AMO_2;
|
||||
DataStall = 1'b1;
|
||||
end else if (MemAccessM & ~DataMisalignedM) begin
|
||||
LSUStall = 1'b1;
|
||||
end else if (MemAccessM & ~DataMisalignedMfromLSU) begin
|
||||
NextState = STATE_FETCH;
|
||||
DataStall = 1'b1;
|
||||
LSUStall = 1'b1;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
DataStall = 1'b0;
|
||||
LSUStall = 1'b0;
|
||||
end
|
||||
STATE_FETCH_AMO_1: begin
|
||||
DataStall = 1'b1;
|
||||
LSUStall = 1'b1;
|
||||
if (MemAckW) begin
|
||||
NextState = STATE_FETCH_AMO_2;
|
||||
end else begin
|
||||
@ -247,45 +341,45 @@ module lsu (
|
||||
end
|
||||
end
|
||||
STATE_FETCH_AMO_2: begin
|
||||
DataStall = 1'b1;
|
||||
if (MemAckW & ~StallW) begin
|
||||
LSUStall = 1'b1;
|
||||
if (MemAckW & ~StallWtoLSU) begin
|
||||
NextState = STATE_FETCH_AMO_2;
|
||||
end else if (MemAckW & StallW) begin
|
||||
end else if (MemAckW & StallWtoLSU) begin
|
||||
NextState = STATE_STALLED;
|
||||
end else begin
|
||||
NextState = STATE_FETCH_AMO_2;
|
||||
end
|
||||
end
|
||||
STATE_FETCH: begin
|
||||
DataStall = 1'b1;
|
||||
if (MemAckW & ~StallW) begin
|
||||
LSUStall = 1'b1;
|
||||
if (MemAckW & ~StallWtoLSU) begin
|
||||
NextState = STATE_READY;
|
||||
end else if (MemAckW & StallW) begin
|
||||
end else if (MemAckW & StallWtoLSU) begin
|
||||
NextState = STATE_STALLED;
|
||||
end else begin
|
||||
NextState = STATE_FETCH;
|
||||
end
|
||||
end
|
||||
STATE_STALLED: begin
|
||||
DataStall = 1'b0;
|
||||
if (~StallW) begin
|
||||
LSUStall = 1'b0;
|
||||
if (~StallWtoLSU) begin
|
||||
NextState = STATE_READY;
|
||||
end else begin
|
||||
NextState = STATE_STALLED;
|
||||
end
|
||||
end
|
||||
STATE_PTW_READY: begin
|
||||
DataStall = 1'b0;
|
||||
LSUStall = 1'b0;
|
||||
if (DTLBWriteM) begin
|
||||
NextState = STATE_READY;
|
||||
end else if (MemReadM & ~DataMisalignedM) begin
|
||||
end else if (MemReadM & ~DataMisalignedMfromLSU) begin
|
||||
NextState = STATE_PTW_FETCH;
|
||||
end else begin
|
||||
NextState = STATE_PTW_READY;
|
||||
end
|
||||
end
|
||||
STATE_PTW_FETCH : begin
|
||||
DataStall = 1'b1;
|
||||
LSUStall = 1'b1;
|
||||
if (MemAckW & ~DTLBWriteM) begin
|
||||
NextState = STATE_PTW_READY;
|
||||
end else if (MemAckW & DTLBWriteM) begin
|
||||
@ -298,15 +392,15 @@ module lsu (
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
default: begin
|
||||
DataStall = 1'b0;
|
||||
LSUStall = 1'b0;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
endcase
|
||||
end // always_comb
|
||||
|
||||
// *** for now just pass through size
|
||||
assign Funct3MfromLSU = Funct3M;
|
||||
assign StallWfromLSU = StallW;
|
||||
assign Funct3MfromLSU = Funct3MtoLSU;
|
||||
assign StallWfromLSU = StallWtoLSU;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -35,7 +35,6 @@ module lsuArb
|
||||
input logic [`XLEN-1:0] HPTWPAdr,
|
||||
// to page table walker.
|
||||
output logic [`XLEN-1:0] HPTWReadPTE,
|
||||
output logic HPTWReady,
|
||||
output logic HPTWStall,
|
||||
|
||||
// from CPU
|
||||
@ -65,7 +64,6 @@ module lsuArb
|
||||
input logic SquashSCWfromLSU,
|
||||
input logic DataMisalignedMfromLSU,
|
||||
input logic [`XLEN-1:0] ReadDataWFromLSU,
|
||||
input logic HPTWReadyfromLSU,
|
||||
input logic DataStall
|
||||
|
||||
);
|
||||
@ -159,7 +157,6 @@ module lsuArb
|
||||
assign CommittedM = SelPTW ? 1'b0 : CommittedMfromLSU;
|
||||
assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromLSU;
|
||||
assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromLSU;
|
||||
assign HPTWReady = HPTWReadyfromLSU;
|
||||
// *** need to rename DcacheStall and Datastall.
|
||||
// not clear at all. I think it should be LSUStall from the LSU,
|
||||
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
|
||||
|
||||
@ -128,11 +128,7 @@ module wallypipelinedhart
|
||||
// IMem stalls
|
||||
logic ICacheStallF;
|
||||
logic DCacheStall;
|
||||
logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
|
||||
logic MMUTranslate, MMUReady;
|
||||
logic HPTWRead;
|
||||
logic HPTWReadyfromLSU;
|
||||
logic HPTWStall;
|
||||
|
||||
|
||||
|
||||
// bus interface to dmem
|
||||
@ -145,7 +141,6 @@ module wallypipelinedhart
|
||||
logic [`PA_BITS-1:0] InstrPAdrF;
|
||||
logic [`XLEN-1:0] InstrRData;
|
||||
logic InstrReadF;
|
||||
logic DataStall;
|
||||
logic InstrAckF, MemAckW;
|
||||
logic CommitM, CommittedM;
|
||||
|
||||
@ -162,7 +157,6 @@ module wallypipelinedhart
|
||||
logic [`XLEN-1:0] HRDATAW;
|
||||
|
||||
// IEU vs HPTW arbitration signals to send to LSU
|
||||
logic DisableTranslation;
|
||||
logic [1:0] MemRWMtoLSU;
|
||||
logic [2:0] Funct3MtoLSU;
|
||||
logic [1:0] AtomicMtoLSU;
|
||||
@ -186,87 +180,23 @@ module wallypipelinedhart
|
||||
|
||||
// mux2 #(`XLEN) OutputInput2mux(WriteDataM, FWriteDataM, FMemRWM[0], WriteDatatmpM);
|
||||
|
||||
pagetablewalker pagetablewalker(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.SATP_REGW(SATP_REGW), // already on lsu port
|
||||
.PCF(PCF), // add to lsu port
|
||||
.MemAdrM(MemAdrM), // alreayd on lsu port
|
||||
.ITLBMissF(ITLBMissF), // add to lsu port
|
||||
.DTLBMissM(DTLBMissM), // already on lsu port convert to internal
|
||||
.MemRWM(MemRWM), // already on lsu port
|
||||
.PageTableEntryF(PageTableEntryF), // add to lsu port
|
||||
.PageTableEntryM(PageTableEntryM), // already on lsu port convert to internal
|
||||
.PageTypeF(PageTypeF), // add to lsu port connects to ifu
|
||||
.PageTypeM(PageTypeM), // already on lsu port convert to internal
|
||||
.ITLBWriteF(ITLBWriteF), // add to lsu port connects to ifu
|
||||
.DTLBWriteM(DTLBWriteM), // already on lsu port convert to internal
|
||||
.MMUReadPTE(MMUReadPTE), // from lsu arb convert to internal
|
||||
.MMUReady(MMUReady), // to lsu arb, convert to internal
|
||||
.HPTWStall(HPTWStall), // from lsu arb convert to internal
|
||||
.MMUPAdr(MMUPAdr), // to lsu arb, convert to internal
|
||||
.MMUTranslate(MMUTranslate), // to lsu arb, convert to internal
|
||||
.HPTWRead(HPTWRead), // to lsu arb, convert to internal
|
||||
.WalkerInstrPageFaultF(WalkerInstrPageFaultF), // add to lsu port
|
||||
.WalkerLoadPageFaultM(WalkerLoadPageFaultM), // add to lsu port (to privilege)
|
||||
.WalkerStorePageFaultM(WalkerStorePageFaultM)); // add to lsu port (to privilege)
|
||||
|
||||
|
||||
|
||||
// arbiter between IEU and pagetablewalker
|
||||
lsuArb arbiter(.clk(clk),
|
||||
.reset(reset),
|
||||
// HPTW connection
|
||||
.HPTWTranslate(MMUTranslate),
|
||||
.HPTWRead(HPTWRead),
|
||||
.HPTWPAdr(MMUPAdr),
|
||||
.HPTWReadPTE(MMUReadPTE),
|
||||
.HPTWReady(MMUReady),
|
||||
.HPTWStall(HPTWStall),
|
||||
// CPU connection
|
||||
.MemRWM(MemRWM),
|
||||
.Funct3M(Funct3M),
|
||||
.AtomicM(AtomicM),
|
||||
.MemAdrM(MemAdrM),
|
||||
.WriteDataM(WriteDataM),
|
||||
.StallW(StallW),
|
||||
.ReadDataW(ReadDataW),
|
||||
.CommittedM(CommittedM),
|
||||
.SquashSCW(SquashSCW),
|
||||
.DataMisalignedM(DataMisalignedM),
|
||||
.DCacheStall(DCacheStall),
|
||||
// LSU
|
||||
.DisableTranslation(DisableTranslation),
|
||||
.MemRWMtoLSU(MemRWMtoLSU),
|
||||
.Funct3MtoLSU(Funct3MtoLSU),
|
||||
.AtomicMtoLSU(AtomicMtoLSU),
|
||||
.MemAdrMtoLSU(MemAdrMtoLSU),
|
||||
.WriteDataMtoLSU(WriteDataMtoLSU),
|
||||
.StallWtoLSU(StallWtoLSU),
|
||||
.CommittedMfromLSU(CommittedMfromLSU),
|
||||
.SquashSCWfromLSU(SquashSCWfromLSU),
|
||||
.DataMisalignedMfromLSU(DataMisalignedMfromLSU),
|
||||
.ReadDataWFromLSU(ReadDataWFromLSU),
|
||||
.HPTWReadyfromLSU(HPTWReadyfromLSU),
|
||||
.DataStall(DataStall));
|
||||
|
||||
|
||||
lsu lsu(.clk(clk),
|
||||
.reset(reset),
|
||||
.StallM(StallM),
|
||||
.FlushM(FlushM),
|
||||
.StallW(StallWtoLSU),
|
||||
.StallW(StallW),
|
||||
.FlushW(FlushW),
|
||||
// connected to arbiter (reconnect to CPU)
|
||||
.MemRWM(MemRWMtoLSU), // change to MemRWM
|
||||
.Funct3M(Funct3MtoLSU), // change to Funct3M
|
||||
.AtomicM(AtomicMtoLSU), // change to AtomicMtoLSU
|
||||
.CommittedM(CommittedMfromLSU), // change to CommitttedM
|
||||
.SquashSCW(SquashSCWfromLSU), // change to SquashSCW
|
||||
.DataMisalignedM(DataMisalignedMfromLSU), // change to DataMisalignedM
|
||||
.MemAdrM(MemAdrMtoLSU), // change to MemAdrM
|
||||
.WriteDataM(WriteDataMtoLSU), // change to WriteDataM
|
||||
.ReadDataW(ReadDataWFromLSU), // change to ReadDataW
|
||||
.MemRWM(MemRWM),
|
||||
.Funct3M(Funct3M),
|
||||
.AtomicM(AtomicM),
|
||||
.CommittedM(CommittedM),
|
||||
.SquashSCW(SquashSCW),
|
||||
.DataMisalignedM(DataMisalignedM),
|
||||
.MemAdrM(MemAdrM),
|
||||
.WriteDataM(WriteDataM),
|
||||
.ReadDataW(ReadDataW),
|
||||
|
||||
// connected to ahb (all stay the same)
|
||||
.CommitM(CommitM),
|
||||
@ -308,16 +238,18 @@ module wallypipelinedhart
|
||||
.PMPStoreAccessFaultM(PMPStoreAccessFaultM),
|
||||
|
||||
// connected to hptw. Move to internal.
|
||||
.PageTableEntryM(PageTableEntryM),
|
||||
.PageTypeM(PageTypeM),
|
||||
.DTLBWriteM(DTLBWriteM), // from hptw.
|
||||
.DTLBMissM(DTLBMissM), // to hptw from dmmu
|
||||
.DisableTranslation(DisableTranslation), // from hptw to dmmu
|
||||
.HPTWReady(HPTWReadyfromLSU), // from hptw, remove
|
||||
.PCF(PCF),
|
||||
.ITLBMissF(ITLBMissF),
|
||||
.PageTableEntryF(PageTableEntryF),
|
||||
.PageTypeF(PageTypeF),
|
||||
.ITLBWriteF(ITLBWriteF),
|
||||
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
||||
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
|
||||
.WalkerStorePageFaultM(WalkerStorePageFaultM),
|
||||
|
||||
.DTLBHitM(DTLBHitM), // not connected remove
|
||||
|
||||
.DataStall(DataStall)) // change to DCacheStall
|
||||
.DCacheStall(DCacheStall)) // change to DCacheStall
|
||||
;
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user