forked from Github_Repos/cvw
Removed the TranslationVAdrQ as it is not necessary.
This commit is contained in:
Ross Thompson
parent
1131ec8e35
commit
a252416535
@ -7,19 +7,19 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -expand -group alu -divider internals
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -243,6 +243,7 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DisableTranslation
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemRWM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DataStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW
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@ -293,7 +294,42 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUTranslate
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add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/pagetablewalker/WalkerState
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add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/pagetablewalker/HPTWStall
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/HPTWRead
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/EndWalk
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add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/MMUReadPTE
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add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/PRegEn
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add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/CurrentPTE
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add wave -noupdate -expand -group ptwalker -divider data
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/TranslationPAdr
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/ValidPTE
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/LeafPTE
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/TranslationPAdr
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageTableEntry
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageType
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/ITLBWriteF
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/DTLBWriteM
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerInstrPageFaultF
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerLoadPageFaultM
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerStorePageFaultM
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/MMUStall
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add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/EndWalk
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add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr
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add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState
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add wave -noupdate -expand -group {LSU ARB} -color {Medium Orchid} /testbench/dut/hart/arbiter/SelPTW
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add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/pagetablewalker/MMUStall
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWTranslate
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWRead
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWPAdr
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReadPTE
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add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReady
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add wave -noupdate -expand -group {LSU ARB} -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
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add wave -noupdate /testbench/dut/hart/lsu/DataStall
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add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
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add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
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@ -320,6 +356,7 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
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add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
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add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate /testbench/dut/hart/pagetablewalker/StartWalk
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add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/DisableTranslation
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add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/VirtualAddress
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add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/CAMHit
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@ -330,8 +367,8 @@ add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/TLBWr
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add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/PTEWriteVal
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add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/WriteLines
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 8} {4545 ns} 0} {{Cursor 3} {2540 ns} 0} {{Cursor 4} {681 ns} 0}
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quietly wave cursor active 2
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WaveRestoreCursors {{Cursor 8} {4545 ns} 0} {{Cursor 3} {3377 ns} 0} {{Cursor 4} {3215 ns} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 189
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configure wave -justifyvalue left
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@ -346,4 +383,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {2313 ns} {2789 ns}
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WaveRestoreZoom {4209 ns} {4657 ns}
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@ -72,7 +72,6 @@ module pagetablewalker
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// Internal signals
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// register TLBs translation miss requests
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logic [`XLEN-1:0] TranslationVAdrQ;
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logic ITLBMissFQ, DTLBMissMQ;
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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@ -110,6 +109,8 @@ module pagetablewalker
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statetype WalkerState, NextWalkerState;
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logic PRegEn;
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logic SelDataTranslation;
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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@ -118,13 +119,8 @@ module pagetablewalker
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assign MemStore = MemRWM[0];
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// Prefer data address translations over instruction address translations
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assign TranslationVAdr = (DTLBMissM) ? MemAdrM : PCF; // *** need to register TranslationVAdr
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flopenr #(`XLEN)
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TranslationVAdrReg(.clk(clk),
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.reset(reset),
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.en(StartWalk), // *** use enable later to save power
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.d(TranslationVAdr),
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.q(TranslationVAdrQ));
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assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr
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assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
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flopenrc #(1)
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DTLBMissMReg(.clk(clk),
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@ -227,7 +223,7 @@ module pagetablewalker
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PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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@ -256,7 +252,7 @@ module pagetablewalker
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PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00;
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]};
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TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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end else begin
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NextWalkerState = FAULT;
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end
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@ -281,8 +277,8 @@ module pagetablewalker
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assign MegapageMisaligned = |(CurrentPPN[9:0]);
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assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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assign VPN1 = TranslationVAdrQ[31:22];
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assign VPN0 = TranslationVAdrQ[21:12];
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assign VPN1 = TranslationVAdr[31:22];
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assign VPN0 = TranslationVAdr[21:12];
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@ -372,7 +368,7 @@ module pagetablewalker
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((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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@ -409,7 +405,7 @@ module pagetablewalker
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((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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else if (ValidPTE && ~LeafPTE) begin
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@ -446,7 +442,7 @@ module pagetablewalker
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((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end
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// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
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@ -478,7 +474,7 @@ module pagetablewalker
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((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
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DTLBWriteM = DTLBMissMQ;
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ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
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TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0];
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TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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end else begin
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NextWalkerState = FAULT;
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end
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@ -516,10 +512,10 @@ module pagetablewalker
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assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme
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assign VPN3 = TranslationVAdrQ[47:39];
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assign VPN2 = TranslationVAdrQ[38:30];
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assign VPN1 = TranslationVAdrQ[29:21];
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assign VPN0 = TranslationVAdrQ[20:12];
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assign VPN3 = TranslationVAdr[47:39];
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assign VPN2 = TranslationVAdr[38:30];
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assign VPN1 = TranslationVAdr[29:21];
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assign VPN0 = TranslationVAdr[20:12];
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// Capture page table entry from ahblite
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