forked from Github_Repos/cvw
fixing coremark branch prediction
This commit is contained in:
parent
d0ddb5f461
commit
041439c008
wally-pipelined
@ -93,7 +93,7 @@ add wave -divider RAM
|
||||
add wave -hex -r /testbench/dut/uncore/dtim/RAM
|
||||
add wave -divider Misc
|
||||
add wave -divider
|
||||
#add wave -hex -r /testbench/*
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
@ -111,5 +111,6 @@ set DefaultRadix hexadecimal
|
||||
-- Run the Simulation
|
||||
#run 7402000
|
||||
#run 12750
|
||||
run -all
|
||||
#run -all
|
||||
run 3000
|
||||
#quit
|
||||
|
@ -91,6 +91,12 @@ module testbench();
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
/* verilator lint_on STMTDLY */
|
||||
|
Loading…
Reference in New Issue
Block a user