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1633 Commits

Author SHA1 Message Date
Ross Thompson
cc605a1966 Bit width error. 2022-10-24 13:48:47 -05:00
Ross Thompson
270a83352f Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks. 2022-10-23 13:46:50 -05:00
Ross Thompson
54bd1fb806 Small cleanup of interlockfsm. 2022-10-22 16:29:51 -05:00
Ross Thompson
f9a04c13df comment updates. 2022-10-22 16:28:44 -05:00
Ross Thompson
78586c5a7a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-22 16:27:30 -05:00
Ross Thompson
611ea6882d Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline. 2022-10-22 16:27:20 -05:00
Jacob Pease
1f207bcafb Extended rxfifotimeout count to actually be 4 characters long. 2022-10-20 17:35:49 -05:00
Ross Thompson
e5cae3bfa0 Moving interlockfsm changes to a temporary branch. 
reduced complexity of cache mux controls.
 2022-10-19 15:08:23 -05:00
Ross Thompson
5ad3ee6b54 Broken don't use this state. 2022-10-19 14:31:22 -05:00
Ross Thompson
de1e569ee9 Noted possible bug with endianness during hptw. 
Minor complexity reduction in interlockfsm.  I think there is a lot of room to simplify.
 2022-10-19 12:20:19 -05:00
Ross Thompson
61f7bad739 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-18 15:06:09 -05:00
Ross Thompson
962ba5e4b8 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
a7ae593a68 Possible fix for interrupt during a floating point divide. 2022-10-18 15:04:21 -05:00
Ross Thompson
2c80c2b35f Merged cacheable with seluncachedadr. 2022-10-17 13:29:21 -05:00
amaiuolo
a0712d1456 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-10-13 22:36:57 +00:00
amaiuolo
000117fcd4 added amaiuolo@hmc.edu 2022-10-13 22:36:52 +00:00
Ross Thompson
47915421c2 Fixed uncached read bug introduced by yesterday's changes. 2022-10-13 11:11:36 -05:00
Ross Thompson
fccaad7f3f Fixed LSU to correctly handle the difference between LLEN and AHBW. 2022-10-12 12:06:15 -05:00
Ross Thompson
12a6a9f83b Actually fixed the bus width issue coming out of the cache. 
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
 2022-10-12 11:33:10 -05:00
Kip Macsai-Goren
f711eb0bcf quick fix to endianness wapping 64 bit reads in 32 bit confgs 2022-10-11 23:08:02 +00:00
Ross Thompson
b2f71b8255 Modified LSU to support DTIM without CSRs. 2022-10-11 14:05:20 -05:00
Ross Thompson
a5c15fd801 Fixed first problem with the rv64i IROM. 2022-10-11 11:35:40 -05:00
David Harris
36c0e1d4e9 Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU 2022-10-10 10:22:12 -07:00
David Harris
e4c5754b3a Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width 2022-10-10 09:10:55 -07:00
David Harris
a5a922d048 Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing 2022-10-10 07:12:37 -07:00
David Harris
6092ca757a New fdivsqrtqsel4cmp module based on comparators rather than table lookup 2022-10-09 04:47:44 -07:00
David Harris
dceb6f9034 Moved shift into divsqrt stage and cleaned up comments 2022-10-09 04:45:45 -07:00
David Harris
55e4911cf0 fdivsqrt code cleanup 2022-10-09 03:37:27 -07:00
Ross Thompson
382ccf74a5 Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS. 2022-10-05 15:46:53 -05:00
Ross Thompson
62951ec653 Fixed wally32e. 2022-10-05 15:37:01 -05:00
Ross Thompson
2144343c4a Name clarifications. 2022-10-05 15:36:56 -05:00
Ross Thompson
2e578eb8d8 Fixed bug with combined dtim+bus. 2022-10-05 15:16:01 -05:00
Ross Thompson
b52ab91028 Possibly have working dtim + bus config. 2022-10-05 15:08:20 -05:00
Ross Thompson
a0c5833d6d Fixed bug in EBU. 2022-10-05 14:51:12 -05:00
Ross Thompson
68aa1434b4 Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS. 
Don't use this commit as the rv32i tests are not passing.
 2022-10-05 14:51:02 -05:00
Ross Thompson
e6b36d0c02 Optimized the ebu's beat counting. 2022-10-05 10:58:23 -05:00
Ross Thompson
3f59ea6b6d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-04 17:38:49 -05:00
Ross Thompson
92d7be645b Reordered the eviction and fetch in cache so it follows a more logical order. 2022-10-04 17:36:07 -05:00
Ross Thompson
52e8e0f5ef Modified cache lru to not have the delayed write. 2022-10-04 15:14:58 -05:00
Kip Macsai-Goren
2bbcec680f addded renamed file 2022-10-04 17:37:05 +00:00
Kip Macsai-Goren
c4441eb0fa Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
175e824a61 Renamed endianswap to match module name 2022-10-04 17:33:49 +00:00
Ross Thompson
56cc04316c Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered. 2022-10-02 16:21:21 -05:00
Ross Thompson
02ed8fc301 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-01 15:01:22 -05:00
Ross Thompson
bc94f4aef1 Disable IFU bus access on TrapM. 2022-10-01 14:54:16 -05:00
Ross Thompson
e6db1c5cf8 Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage. 2022-09-29 18:37:34 -05:00
David Harris
fc4146f409 Adding start signals for integer divider to fdivsqrt 2022-09-29 16:30:25 -07:00
Ross Thompson
47e936cab3 Renamed signals in EBU. 2022-09-29 18:29:38 -05:00
cturek
c72e2e5d49 Added integer inputs and flags to divsqrt 2022-09-29 23:08:27 +00:00
Ross Thompson
f9c4b32bd5 Simplification to EBU. 2022-09-29 18:06:34 -05:00
Ross Thompson
146ff6ff6a Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore. 2022-09-29 11:54:03 -05:00
Ross Thompson
638e506d0b Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache. 2022-09-28 17:39:51 -05:00
Ross Thompson
87485ed237 Possible fix for ifu/lsu arbiration issue. 2022-09-27 17:24:35 -05:00
Ross Thompson
afc6934249 Possible fix to the bus cache interaction. 2022-09-27 11:34:33 -05:00
Ross Thompson
dfe6bdd06d Found a hidden bug in the cache to bus fsm interlock. 2022-09-26 17:41:30 -05:00
Ross Thompson
f24b0feeed renamed ahbmulticontroller to ebu. 2022-09-26 14:37:18 -05:00
Ross Thompson
fd47cf05c3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-26 12:49:16 -05:00
Ross Thompson
fd2a8e621a Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed. 2022-09-26 12:48:26 -05:00
David Harris
b5d2bbe7ca changed always_ff to always in sram1p1rw to fix testbench complaint 2022-09-25 19:56:40 -07:00
Ross Thompson
dcc00ef4b3 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
 2022-09-23 11:46:53 -05:00
Ross Thompson
6a6686a34b Removed the write first sram model. 2022-09-22 16:12:08 -05:00
Ross Thompson
8a6ca027c2 The valid and dirty bits match the SRAM implementation now. 2022-09-22 16:09:09 -05:00
Ross Thompson
29087812e1 Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
f74d21e063 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 18:24:06 -05:00
Ross Thompson
cd5b8be78f Cleaned up the IFU and LSU around dtim and irom address calculation. 2022-09-21 18:23:56 -05:00
David Harris
cfa83fdd98 For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc 2022-09-21 13:30:35 -07:00
David Harris
f08d5b23d5 Eliminated store after store stall when no cache; simplified divshiftcalc logic. 2022-09-21 13:02:34 -07:00
Ross Thompson
f83d640068 Updated IROMAdr logic. 2022-09-21 12:42:43 -05:00
Ross Thompson
0294ca0469 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 12:36:52 -05:00
Ross Thompson
cdc80c1f28 Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
David Harris
3b0714b059 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 10:35:11 -07:00
David Harris
1c8581dd6d Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest 2022-09-21 10:35:08 -07:00
Ross Thompson
427db1f55f Renamed brom1p1r to rom1p1r. 
removed used file bram2p1r1w.sv.
 2022-09-21 12:31:20 -05:00
Ross Thompson
234cf7510e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 12:20:12 -05:00
Ross Thompson
91fcca9d17 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
d6fa8d51d7 Modified sram1p1rw to support 3 different implementation styles. 
SRAM, Read first, and Write first.
 2022-09-21 11:26:00 -05:00
David Harris
f87e15388a commented SpecialCase 2022-09-21 05:02:08 -07:00
David Harris
b21e36a788 Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc 2022-09-21 04:55:43 -07:00
David Harris
437fd52bf6 Gated sticky bit in fdiv with SpecialCase 2022-09-20 20:05:00 -07:00
David Harris
9c8edb9cb6 renamed u to udigit to avoid conflict with U 2022-09-20 19:29:23 -07:00
cturek
e8f2715a81 Fixed R4 Sqrt overshifting 2022-09-21 00:05:36 +00:00
cturek
49a1259cf9 Fixed fgen4 2022-09-20 20:00:01 +00:00
Ross Thompson
c73fae8a96 Merge branch 'tempMain' into main 2022-09-20 13:57:38 -05:00
Ross Thompson
b2f4d4aaa7 Added chip enables to sram. 2022-09-20 10:49:14 -05:00
Ross Thompson
7470bf7c7c Added comment. 2022-09-20 09:49:53 -05:00
Ross Thompson
ea6b687f7c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-20 09:47:16 -05:00
David Harris
811f498f63 renamed q to u for unified digit selection 2022-09-20 04:35:14 -07:00
David Harris
705a2bd97b Removed D2 and D2b from radix2 stage 2022-09-20 04:20:38 -07:00
David Harris
c77ec2aa9c Simplified UM initialization 2022-09-20 04:18:12 -07:00
David Harris
956011b40b fdivsqrtfgen4 comments 2022-09-20 04:13:21 -07:00
David Harris
8d1408a9d6 Moved fpu modules into subdirectories 2022-09-20 04:12:05 -07:00
David Harris
0af8151c2a Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
David Harris
5b13140078 Simplified fdivsqrtpostproc QmM logic 2022-09-20 03:30:18 -07:00
David Harris
8647de5ee4 make QmM size b+1 indpenedent of radix 2022-09-20 03:25:09 -07:00
David Harris
31c3b62774 clean up divshiftcalc 2022-09-20 03:19:50 -07:00
David Harris
7177745111 clean up divshiftcalc 2022-09-20 03:17:29 -07:00
David Harris
b48bbc4294 clean up divshiftcalc 2022-09-20 03:13:11 -07:00
David Harris
010c88816b clean up divshiftcalc 2022-09-20 03:08:25 -07:00
David Harris
712f1d8d3a Cleaning up divshiftcalc LOGNORMSHIFTSZ 2022-09-20 02:35:01 -07:00
Jacob Pease
c797aee62c Fixed rxfifotimeout restarting for every new character, even when already high. 2022-09-19 18:00:30 -05:00
cturek
85b3e9bfe6 Radix 4 sqrt passing first two tests 2022-09-19 21:26:32 +00:00
Ross Thompson
6a1b909a3f Fixed up IFU ahb interface names and widths. 2022-09-19 10:54:22 -05:00
David Harris
1e6bd26bb6 Removed EarlyTermShift from fdiv 2022-09-19 08:44:23 -07:00
David Harris
a36747fda0 Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
David Harris
34bd82e4a3 fdivsqrtiter simplification 2022-09-19 01:08:01 -07:00
David Harris
b19c37eb0f Reduced number of cycles needed for division 2022-09-19 01:02:04 -07:00
David Harris
7826cf0bcb Cleaned up otfc4 2022-09-19 00:58:20 -07:00
David Harris
6bab8f0e3f OTFC simplification 2022-09-19 00:51:56 -07:00
David Harris
362056f53d Removed unused otfc for Q 2022-09-19 00:43:27 -07:00
David Harris
32028c437c fdiv cleanup 2022-09-19 00:32:34 -07:00
David Harris
b7b082482f Division working again for radix 2 with unified OTFC 2022-09-19 00:30:30 -07:00
David Harris
91194a9c3e Unified on-the-fly conversion working for radix 2; broke radix-4 division 2022-09-19 00:04:00 -07:00
David Harris
9fb3382ec3 Added 2 bits to C to initialize properly 2022-09-18 22:44:22 -07:00
David Harris
33933dd6b0 Added 2 bits to C to initialize properly 2022-09-18 22:42:35 -07:00
Ross Thompson
0fb45cffa1 Removed NonIROM and NonDTIM select signals from IFU and LSU. 2022-09-17 22:01:03 -05:00
Ross Thompson
cc1ba84637 Found the ahb burst bug. 
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests.  It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads.  The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads.  In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
 2022-09-17 20:30:01 -05:00
David Harris
f65d941561 Reduced number of cycles required for lower-precision sqrt 2022-09-17 09:55:34 -07:00
David Harris
54ad15d595 Starting to adust number of cycles for division/sqrt 2022-09-17 05:58:59 -07:00
cturek
f07d4b3481 Fixed j1 to align with new C reg 2022-09-16 02:15:48 +00:00
David Harris
a7b5a0419a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-15 12:49:21 -07:00
David Harris
aa1f3ca2be renamed endianswap 2022-09-15 12:49:18 -07:00
Ross Thompson
4c8ae8b421 Fixed subword read to work with bigendian. 2022-09-15 14:08:04 -05:00
David Harris
877cc63063 FDIVSQRT cleanup 2022-09-15 09:10:57 -07:00
Ross Thompson
db56a326c9 renamed multimanager to multicontroller. 2022-09-14 14:03:37 -05:00
Ross Thompson
a536829824 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-14 13:59:22 -05:00
cturek
5b35473339 Added shift for radix 4 sqrt 2022-09-14 17:34:24 +00:00
cturek
9757d8ce3e Moved X-1 to preproc 2022-09-14 17:26:56 +00:00
cturek
8378d6b871 removed unnecessary XZero from wsmux 2022-09-14 16:59:52 +00:00
David Harris
4038c4faa9 ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-14 09:42:17 -07:00
Ross Thompson
2ae62c2869 pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
Ross Thompson
40e7d2648f Renamed signals in the LSU. 2022-09-13 11:47:39 -05:00
David Harris
2babf1fd7a Removed unused signals 2022-09-12 11:35:35 -07:00
David Harris
f45bb25618 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 16:05:58 -07:00
David Harris
1688d544b9 Moved C to shift before rather than after using in an iteration 2022-09-08 16:05:53 -07:00
David Harris
1c3064af08 divsqrt comment cleanup 2022-09-08 15:40:42 -07:00
Ross Thompson
33ef158ff4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 17:15:46 -05:00
David Harris
e0a9b19008 CSA-based completion detection 2022-09-08 14:58:08 -07:00
Ross Thompson
8618045bf2 Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
Ross Thompson
d12ceb46b0 Oups the ahbinterface.sv was accidentally named abhinterface.sv. 2022-09-08 13:21:37 -05:00
Ross Thompson
fbea27bd69 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 16:36:51 -05:00
Ross Thompson
ae4a55471d Oups fixed order of ending swap with mux between cache and fetch buffer. 2022-09-07 16:29:47 -05:00
David Harris
f628622ea0 Factored out aplusbeq0 unit 2022-09-07 11:36:35 -07:00
David Harris
d91b4de348 Preprocessing cleanup 2022-09-07 10:21:27 -07:00
Ross Thompson
d07c44bcf6 Merge branch 'multimanager' into main 2022-09-07 10:54:27 -05:00
David Harris
29f41c6792 Continued simplifying fdivsqrt postprocessing 2022-09-07 07:02:22 -07:00
David Harris
461b9d370d Continued simplifying fdivsqrt postprocessing 2022-09-07 07:00:13 -07:00
David Harris
825d3169d9 Moving postprocessing into postproc block 2022-09-07 06:42:37 -07:00
David Harris
f40c6b0ec4 fdivsqrtfsm cleanup 2022-09-07 06:32:07 -07:00
David Harris
a0abe48ad2 fdivsqrtfsm cleanup 2022-09-07 06:27:01 -07:00
David Harris
8438546d52 Fixed regression for divsqrt radix2 2022-09-07 06:12:23 -07:00
Ross Thompson
6685b0563e James found a bug in synchronizer. Was not actually back to back flip flops. 2022-09-06 15:06:54 -05:00
Ross Thompson
99e3f55637 Added logic to make burst optional. 2022-09-06 09:21:21 -05:00
Ross Thompson
fcf72bb6ba Added generate around the longer latency version of the ram_ahb.sv 2022-09-06 09:21:03 -05:00
Ross Thompson
20842b38b9 Names changes. 2022-09-05 20:49:35 -05:00
Ross Thompson
4e7a52a7a7 Cleaned up hacks to ram. 2022-09-04 14:52:40 -05:00
Ross Thompson
9d5a7281b8 Modified ram_ahb to work with different latencies. 2022-09-04 14:46:15 -05:00
Ross Thompson
7ae58c6654 Progress towards fixing the select HREADY muxing in uncore. 2022-09-04 13:07:49 -05:00
Ross Thompson
26bfaddb25 Disabled AHB burst mode, which discovered a bug. 
Multimanger bug in how back to back requests were arbitrated.
 2022-09-03 22:31:41 -05:00
Ross Thompson
3e540a3ca3 Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle. 2022-09-02 19:58:41 -05:00
Ross Thompson
4115087b30 Renamed state in buscachefsm to match AHB phases. 2022-09-02 17:17:40 -05:00
Ross Thompson
472fb5e888 Renamed states in busfsm to match AHB phases and book names. 2022-09-02 17:12:36 -05:00
Ross Thompson
15a2fbdd33 Possible fix for AHB trailing ~HREADY bug. 2022-09-02 16:58:35 -05:00
Ross Thompson
851ad4417d Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 16:31:07 -05:00
Ross Thompson
2aa5886769 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
722e1a029e Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 13:54:48 -05:00
Ross Thompson
559e093ab5 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
David Harris
648a3aae09 Initial radix 4 square root debuggin 2022-09-01 16:57:57 -07:00
Ross Thompson
83c427c5b5 clean up subword write. 2022-09-01 17:55:19 -05:00
David Harris
247ce70348 Fixed lint errors in square root and improved waveforms in testfloat 2022-09-01 15:49:13 -07:00
Ross Thompson
5b4e744972 marked possible improvement to ahb bus fsms. 2022-08-31 23:57:08 -05:00
David Harris
8fad5073cd fdiv debug 2022-08-31 14:26:31 -07:00
Ross Thompson
5c8631fd16 Reduced busfsm to 3 states! 2022-08-31 16:11:59 -05:00
Ross Thompson
1cd7d8dbfe Simplified. 2022-08-31 15:40:56 -05:00
Ross Thompson
2b528dc8be more renaming. 2022-08-31 14:52:06 -05:00
Ross Thompson
ab4c75cbf5 More renaming. 2022-08-31 14:49:08 -05:00
Ross Thompson
6e85f850a4 Moved files. 
Encapsulated ahbinterface.
 2022-08-31 14:45:01 -05:00
Ross Thompson
fcd1465de1 Renamed AHBCachebusdp to abhcacheinterface. 2022-08-31 14:12:19 -05:00
Ross Thompson
d6d1c5d66d Moved files around. 2022-08-31 14:08:06 -05:00
Ross Thompson
6912656aab Merge branch 'multimanager' into main 2022-08-31 13:10:22 -05:00
Ross Thompson
39c2cad9af Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-31 13:10:04 -05:00
David Harris
e64f41f199 Checking in radix 4 square root with qsel, fgen, softc, but not working 2022-08-31 10:54:50 -07:00
Ross Thompson
08d0c1cc83 Major cleanup of multimanager. 2022-08-31 12:40:25 -05:00
Ross Thompson
352f7443c2 Cleanup multimanager. 2022-08-31 12:04:44 -05:00
Ross Thompson
d06c64094b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-31 11:38:29 -05:00
Ross Thompson
1e752c1268 cleanup of multimanager. 2022-08-31 11:38:06 -05:00
Ross Thompson
1663f571ed More Cleanup. 2022-08-31 11:21:02 -05:00
Ross Thompson
68e54977fe More cleanup. 2022-08-31 11:12:38 -05:00
Ross Thompson
0b41ed63f1 More simplifications. 2022-08-31 10:45:16 -05:00
Ross Thompson
ddd9c507fe Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier. 2022-08-31 10:36:30 -05:00
Ross Thompson
6122c03e39 Removed unused old versions of the bus controllers. 2022-08-31 09:51:54 -05:00
Ross Thompson
1c248e5164 Removed old signals. 2022-08-31 09:50:39 -05:00
Ross Thompson
5b8f888e21 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
96793d15c0 more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
63a824cca1 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
a532eb61ba Progress. 2022-08-30 14:17:00 -05:00
David Harris
5956fbdd62 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
Ross Thompson
c8a5d61cbb new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00
Ross Thompson
5eb1fff27d Have a rough working multi manager! 2022-08-29 17:11:27 -05:00
Ross Thompson
4f40bd07c3 Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu. 2022-08-29 17:04:53 -05:00
David Harris
cb54e95285 commented out lines to have divider work again 2022-08-29 13:01:32 -07:00
David Harris
758b177067 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 12:01:13 -07:00
David Harris
7b0e43bc10 Initial FDIVSQRT simplification working 2022-08-29 12:01:09 -07:00
Ross Thompson
4d7b905806 Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager. 2022-08-29 13:01:24 -05:00
Ross Thompson
40cf4a9ea9 Typo. 2022-08-29 11:40:35 -05:00
Ross Thompson
1c9aed2e7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 11:38:37 -05:00
Ross Thompson
9a7c7e8398 Added comments about planned changes. 2022-08-29 09:48:00 -05:00
David Harris
16cde5f87e Simplify FSM 2022-08-29 04:32:27 -07:00
David Harris
6961e499dc Renamed special case 2022-08-29 04:29:58 -07:00
David Harris
81ec1ac858 Separated out radix 2 and radix 4 stages into different modules 2022-08-29 04:26:14 -07:00
David Harris
b4cb9a678a renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
Ross Thompson
35d0b759d1 Removed ignore request from busfsm. 2022-08-28 21:12:27 -05:00
Ross Thompson
dd00474956 Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
Ross Thompson
e3e1f29428 Reordered the adrdecs. 2022-08-28 13:38:57 -05:00
Ross Thompson
99e0e5c817 Possible fix. 2022-08-28 13:10:47 -05:00
Ross Thompson
5e77b1bd2b Partial fix to bus + dtim. 2022-08-27 23:44:17 -05:00
David Harris
35d0a951d2 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
David Harris
3959902c5b Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus 2022-08-27 05:31:56 -07:00
David Harris
bd6f2444cd Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00
David Harris
76006825b3 Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
David Harris
921a49921b Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
460a95f99b Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
David Harris
6409548c8b Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
906f6f2990 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
David Harris
841eae58ca Fixed endian swapping on bus only 2022-08-26 19:58:04 -07:00
David Harris
af2e71046e Fixed rv32e LSU and IFU issues 2022-08-25 20:02:38 -07:00
David Harris
8cbdbb1c38 lsu simplification 2022-08-25 18:52:42 -07:00
David Harris
d507bb3d70 busfsm simplified 2022-08-25 18:36:53 -07:00
David Harris
dc52f55aa6 Removed unused signals 2022-08-25 18:34:39 -07:00
David Harris
50826c0b61 Removed unused signals 2022-08-25 18:30:46 -07:00
David Harris
7cbca2dd22 Removed UncachedBusRead and UncachedBusWrite 2022-08-25 18:24:39 -07:00
David Harris
845807a329 Restored ahbtranstype 2022-08-25 18:22:26 -07:00
David Harris
4ab678ed48 Removed ahbtranstype 2022-08-25 18:21:45 -07:00
David Harris
f405a191af Removed WordCountFlag 2022-08-25 18:21:18 -07:00
David Harris
db7698202d Removed UncachedAccess 2022-08-25 18:20:52 -07:00
David Harris
7801ed48b3 Removed UncachedRW 2022-08-25 18:19:41 -07:00
David Harris
bb4ae908db Removed CacheBusAck 2022-08-25 18:17:34 -07:00
David Harris
85b5587678 Removed SelUncachedAdr 2022-08-25 18:15:59 -07:00
David Harris
555083b0c3 Removed Cache_Enabled 2022-08-25 18:13:34 -07:00
David Harris
b982db5bd5 Removed STATE_BUS_FETCH and STATE_BUS_WRITE 2022-08-25 18:12:09 -07:00
David Harris
de9ec7cc2e Removed CacheFetchLine and CacheWriteLine 2022-08-25 18:10:15 -07:00
David Harris
fb5ddc476c Removed CountEn 2022-08-25 18:05:44 -07:00
David Harris
7eae6765df Removed wordcount 2022-08-25 18:04:49 -07:00
David Harris
73419f0d41 Added buscachefsm for system with bus and cache 2022-08-25 18:01:01 -07:00
David Harris
0b918d6916 Separated busdp for cache from simpler logic for no cache 2022-08-25 17:54:04 -07:00
David Harris
5c1934208a Simplified swbytemask 2022-08-25 17:32:16 -07:00
David Harris
352bf88ac0 FIxed wallypipelinedsoc merge conflict 2022-08-25 15:36:47 -07:00
David Harris
b96942e84c Removed delayed AHB signals from top level 2022-08-25 15:34:14 -07:00
Ross Thompson
109bcd470e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
Ross Thompson
e70c90d351 Finally resolved the issues with the rv32ic and rv64ic configurations. 2022-08-25 16:00:55 -05:00
Ross Thompson
ad3e632119 Almost fixed issues with irom and dtim address selection. 2022-08-25 15:52:25 -05:00
David Harris
6222e15946 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
32f86b1b6b Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
David Harris
f782fe9367 Fixed brom name 2022-08-25 12:48:00 -07:00
Ross Thompson
bbf668e460 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:45:02 -05:00
David Harris
5b3c68fe74 ahblite cleanup 2022-08-25 12:44:25 -07:00
Ross Thompson
502eb0f5d1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:40:52 -05:00
David Harris
d7be94fab2 Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
David Harris
7a129af9ad Removed M sufix from busdp signals 2022-08-25 11:13:01 -07:00
David Harris
84ba62a04c Renamed LSUFunct3M to Funct3 in busdp 2022-08-25 11:08:12 -07:00
David Harris
78618f5fc0 Renaming LSU signals from busdp 2022-08-25 11:05:10 -07:00
David Harris
cd02c894df renamed BusBuffer to FetchBuffer 2022-08-25 10:44:39 -07:00
David Harris
5dc4fb757a Continued busdp/ebu simplification 2022-08-25 10:20:02 -07:00
David Harris
24ce72f0a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:52:49 -07:00
David Harris
89860588b8 Renamed AHB signals coming out of LSU to LSH_<AHBNAME> 2022-08-25 09:52:08 -07:00
Ross Thompson
bd9401179d BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
5cc4f1f1cd Added generate around uncore. 2022-08-25 10:35:24 -05:00
Ross Thompson
1e1646da90 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
72b886ec8f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:03:34 -05:00
Ross Thompson
bc0edc7bdf Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
David Harris
4ecdbb308a Renamed DCache to Cache in busdp/busfsm signal interface 2022-08-25 06:21:22 -07:00
David Harris
b9dc8d9e33 Cleanup typos 2022-08-25 04:32:19 -07:00
David Harris
cb2c0fe027 Minor name cleanups 2022-08-25 04:28:25 -07:00
David Harris
a3828420c0 Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM 2022-08-25 04:06:27 -07:00
David Harris
fe3147806d removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
David Harris
b3a13a01f8 Stripped write capaibilty out of rom_ahb 2022-08-24 17:23:08 -07:00
David Harris
e6077f1f16 Added ROM module and moved memories into generic/mem 2022-08-24 17:03:22 -07:00
David Harris
1ef0c7c2be Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-24 16:30:28 -07:00
David Harris
9d5468887e Ram cleanup 2022-08-24 16:30:25 -07:00
Ross Thompson
b650d7e05a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
c636387613 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
012559169b Fixed lint errors with bram wrapper. 2022-08-24 13:19:23 -05:00
Ross Thompson
c6927d2ace Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
e2138d8d0f bram synthesis test 2022-08-23 19:34:45 -07:00
Ross Thompson
0c52c7f69c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 18:52:15 -05:00
Ross Thompson
ee3d968da0 Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite. 2022-08-23 18:51:11 -05:00
David Harris
8d48ff4e63 Fixed FPU-IEU forwarding stall 2022-08-23 14:14:41 -07:00
David Harris
8b2e368805 Only stall FPU to IEU on convert instructions with dependencies 2022-08-23 12:57:18 -07:00
David Harris
113258a0d0 Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
David Harris
69be6d0873 Simplify IEU-FP datapath 2022-08-23 11:16:36 -07:00
David Harris
746842107b Improved illegal instruction checking in FPU 2022-08-23 11:08:02 -07:00
David Harris
27cca2e3fd Fixed LSU typos 2022-08-23 10:23:08 -07:00
David Harris
46f30d3dbe Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 10:14:59 -07:00
David Harris
13831aa3d3 typo in srtfsm 2022-08-23 10:14:54 -07:00
Katherine Parry
f9aa94f87b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-23 16:36:32 +00:00
Katherine Parry
72a54ef621 renamed rounding bits to L,G,R,S and fixed lint warning 2022-08-23 16:36:20 +00:00
Ross Thompson
7080fe7788 Reversed order of supported sized in adrdecs. 2022-08-23 11:14:53 -05:00
Ross Thompson
b0606a1699 Replaced FPU data replicaiton on WriteData bus with 0 extention. 2022-08-23 10:46:03 -05:00
Ross Thompson
b9fadc11c3 Replaced LSU data replication with 0 extention. 2022-08-23 10:43:47 -05:00
Ross Thompson
cd0da2e3b3 Updated the names of the *WriteDataM inside the LSU to more meaningful names. 
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
 2022-08-23 10:34:39 -05:00
David Harris
7c91ed38a3 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
a9a5285ba8 Named HTRANS states in busfsm 2022-08-22 13:56:46 -07:00
David Harris
24a05c35d9 Renamed signals for LSU - FPU interface 2022-08-22 13:47:56 -07:00
David Harris
13d863a810 renamed GrantData to LSUGrant 2022-08-22 13:47:19 -07:00
David Harris
34eece10b8 Finished FPU-LSU interface cleanup 2022-08-22 13:43:04 -07:00
David Harris
7151befd04 Removed FStore2 and simplified HPTW 2022-08-22 13:29:54 -07:00
David Harris
bf54c1c868 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:29:20 -07:00
David Harris
fffad8b314 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-22 13:28:54 -07:00
David Harris
2170203847 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:28:51 -07:00
Katherine Parry
a1f0c6c598 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-22 17:16:25 +00:00
Katherine Parry
1accb92745 sqrt passes - lint warnings remain 2022-08-22 17:16:12 +00:00
David Harris
564281b8c1 Removed 2-cycle FPU-IEU latency stall 2022-08-22 16:14:15 +00:00
David Harris
1404d1c248 moved CSA to generic 2022-08-22 08:41:23 +00:00
David Harris
a8870b70b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-22 08:28:31 +00:00
David Harris
b91f33372e Commented out unused comparators 2022-08-22 08:28:28 +00:00
Ross Thompson
88d34d0f56 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-21 16:03:11 -05:00
Ross Thompson
21526957cf Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
92c3cdc27d Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation. 2022-08-21 15:28:29 -05:00
Ross Thompson
a049f456e8 Removed logic from Verilog wrapper. 2022-08-21 14:07:43 -05:00
Katherine Parry
617dc02d01 fixed -1 issue in division 2022-08-20 00:53:45 +00:00
Ross Thompson
96d6218078 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
5301444a61 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
970a90dd72 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
c3bd396bdb Removed old code from interlockfsm. 2022-08-17 12:52:56 -05:00
Katherine Parry
0f077012c3 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
8eeca3319c radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
Katherine Parry
8f1d8669b0 fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
David Harris
b13cdf79b3 FMA cleanup 2022-08-02 07:42:32 -07:00
David Harris
baeafc4fd2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-02 07:34:12 -07:00
David Harris
d3e39763b6 Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
Ross Thompson
acd920ae2f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 22:09:11 -05:00
Ross Thompson
f7e64fcd69 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
David Harris
0482bf4fc0 merged lza back into main 2022-08-01 19:45:21 -07:00
David Harris
0b95ca129c Fixed fmaadd to work with new LZA 2022-08-01 19:40:55 -07:00
Ross Thompson
b8356c7449 Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris. 2022-08-01 21:12:25 -05:00
Ross Thompson
171cf7413b Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
Ross Thompson
5d9dab6149 pulled swbbytemask out of subword write. 2022-08-01 20:48:45 -05:00
David Harris
8b44037f58 Parameterized fmalza 2022-08-01 16:18:02 -07:00
David Harris
6e78b46761 Completed LZA simplificaiton 2022-08-01 16:13:16 -07:00
David Harris
76021769a7 lza cleanup 2022-08-01 16:01:02 -07:00
David Harris
47d204f4a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 15:47:58 -07:00
David Harris
c8d4f3a542 lza cleanup 2022-08-01 15:47:03 -07:00
David Harris
c531df9c4e lza cleanup 2022-08-01 15:43:48 -07:00
David Harris
5468a90cf3 lza cleanup 2022-08-01 15:40:12 -07:00
David Harris
4953ccf273 lza cleanup 2022-08-01 15:37:09 -07:00
Katherine Parry
66eca28ccd regression passes fpu tests 2022-08-01 19:56:25 +00:00
Katherine Parry
9672f5451a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 19:55:50 +00:00
David Harris
31215277ee more lza cleanup 2022-08-01 12:34:00 -07:00
David Harris
48500c642c LZA cleanup 2022-08-01 12:30:42 -07:00
David Harris
87e6402af6 LZA refactoring switched to Pp1, Gm1, Km1 2022-08-01 12:20:23 -07:00
David Harris
5012b96120 LZA refactoring 2022-08-01 11:36:21 -07:00
Katherine Parry
75f39e0c5b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 18:35:07 +00:00
David Harris
231f52c1fd fmalza edits to match textbook 2022-08-01 18:23:39 +00:00
David Harris
e3b970d3ff Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
Ross Thompson
01359dbc4b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-31 12:48:51 -05:00
Katherine Parry
de03954946 re-added FStore2 in Cache 2022-07-29 22:54:49 +00:00
David Harris
d2de84a456 Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
Ross Thompson
f1bd2524b7 Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
Ross Thompson
334008630f Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
856ac24686 Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
458bfbf6f6 Merged evict dirty clear with flush write back. 2022-07-24 00:22:43 -05:00
Ross Thompson
70032bf8f4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Ross Thompson
5cd6c8069d signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
7d026e02f2 cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
706bc819e1 cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
0f586c9ed3 Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Katherine Parry
bd336f18b3 merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
slmnemo
5b71ceac5c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
0bfc3fda1b Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Katherine Parry
ee7932c804 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
David Harris
07c946bb04 Reset MSR on read 2022-07-22 04:29:27 +00:00
slmnemo
bfa500234d Fixed UART bug related to parity and MSR/LSR 2022-07-21 20:35:46 -07:00
Katherine Parry
270216dd02 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Katherine Parry
67c99d3d1a added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
Katherine Parry
e8c9830b88 turn off 2 word store durring non-fp instructions 2022-07-20 21:57:23 +00:00
Ross Thompson
9868e685a4 Minor cleanup of cache. 2022-07-19 23:04:23 -05:00
Ross Thompson
6c8ac7851e Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction. 2022-07-19 22:42:25 -05:00
Katherine Parry
fb890d621d moved ctrl signal registers into fctrl, also a lot of code cleaning 2022-07-20 02:27:39 +00:00
cturek
db39a05abc small changes 2022-07-20 01:36:25 +00:00
Katherine Parry
afcddf7035 oprimized zeros and replaced complex ?: with always_comb 2022-07-19 23:44:37 +00:00
Ross Thompson
ffda64587c Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Katherine Parry
4c2afbbc4f moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
a590728350 reworked fmashiftcalc to match book 2022-07-19 00:04:24 +00:00
David Harris
59eb11b73a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 23:11:12 +00:00
Katherine Parry
e599f82b29 moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
921debf930 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
ea7b32a50b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 17:31:29 +00:00
Katherine Parry
5bb1478859 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
Ross Thompson
a88543275f Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
3670c47141 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
David Harris
7c744f0053 Rewrote convert shift calculation with always for ease of reading 2022-07-17 16:40:58 +00:00
David Harris
6e1d4ec4ed restored intPending logic to be sticky for PLIC 2022-07-16 17:43:31 -07:00
Katherine Parry
a4cd157f00 forgot some files 2022-07-15 21:42:45 +00:00
Katherine Parry
e251022269 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
Katherine Parry
b069cfbec2 fixed error in divsqrt 2022-07-14 18:16:00 +00:00
Katherine Parry
e5a8ac2a44 renamed a file to fit diagram 2022-07-13 23:44:54 +00:00
Katherine Parry
7e163e22a3 some code cleanup 2022-07-13 15:28:22 -07:00
Katherine Parry
77ea4e47cb removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
Katherine Parry
26e39dd325 removed the +1 in the cvt 2022-07-13 09:41:35 -07:00
Katherine Parry
e05b2a07d2 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
452b017f9a found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
5c0ecfa433 forgot a file 2022-07-11 18:31:51 -07:00
Katherine Parry
7815b81716 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
b728e5054d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
David Harris
2bc8ff555b added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
9cb675b2e4 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
Katherine Parry
3476579e02 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
9ef45f36fd renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
James Stine
c5dfefe669 Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
David Harris
c72e4d43d2 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 09:09:07 +00:00
David Harris
381f3298d8 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
1ce0975366 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
9b6d9666c5 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
Katherine Parry
905b7ffc84 moved unsused division code again 2022-07-07 16:41:26 -07:00
Katherine Parry
2bbde827e6 Revert "moved old divsqrt to unusedsrc" 
This reverts commit c9f5ae12ea.
 2022-07-07 16:29:17 -07:00
Katherine Parry
c9f5ae12ea moved old divsqrt to unusedsrc 2022-07-07 16:09:56 -07:00
Katherine Parry
41c16be012 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
David Harris
96a75d7749 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
08769e35ae modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
2f342c430e fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
David Harris
88e3233935 Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
David Harris
08ae2db080 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:43:05 +00:00
Ross Thompson
bd46cf76a9 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
cb33d2289b fixed width mismatch for rv64 ieuadrM and readdatawordM 2022-07-06 22:39:35 +00:00
David Harris
9ef38145d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 13:26:26 +00:00
David Harris
a599084b88 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye
846f12aa2e new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye
01e6d69a67 took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye
50e9b6ac53 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
David Harris
d73645944f APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
d033659beb Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
e7fe7ad0c8 AHB bridge for gpio 2022-07-05 05:01:59 +00:00
David Harris
4723ff559c Added reference to Schmookler01 for LOA 2022-07-05 05:01:12 +00:00
David Harris
aa3dc8bfe1 Added comments to PLIC about likely bug 2022-07-05 05:00:29 +00:00
David Harris
4c48d71e4b removed delay in ahblite 2022-07-05 04:59:28 +00:00
Katherine Parry
010a05f583 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
1b4584e825 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
David Harris
bde1c5eb1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-02 19:37:14 +00:00
David Harris
52dbc9f8be FMA ZAligned name 2022-07-02 19:35:13 +00:00
Katherine Parry
575b73fa8c some prostprocessing cleanup 2022-07-01 14:55:46 -07:00
Katherine Parry
6baded9121 added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Katherine Parry
f2d05911ca very basic early termination passes testfloat 64-bit tests 2022-06-28 00:16:22 +00:00
Katherine Parry
f25bb4a384 radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
2d5d1f4e8f radix-4 divider passing all double precision testfloat tests 2022-06-27 17:04:51 +00:00
Katherine Parry
06f7f9b147 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
Katherine Parry
d16ae7c305 passing regression again 2022-06-25 00:31:32 +00:00
Katherine Parry
913a381442 commented out error - also some divider bugs fixed 2022-06-25 00:04:53 +00:00
Katherine Parry
c1b4e7fd2c modified result select to account for x/inf 2022-06-24 21:23:15 +00:00
Katherine Parry
a65c0eb679 radix 4 division denormal result handeling 2022-06-24 21:02:50 +00:00
Katherine Parry
d058ec6329 added denormal input handeling - radix 4 2022-06-24 19:41:40 +00:00
Katherine Parry
fc75fc633f division by zero added 2022-06-24 01:09:44 +00:00
Katherine Parry
86cdbd90e6 forgot a file 2022-06-23 23:01:30 +00:00
Katherine Parry
97ded2cdd9 div debug - accounted for 1 bit normalization in exponent calculation 2022-06-23 22:59:43 +00:00
Katherine Parry
d17596353b lint warning fix 2022-06-23 22:37:44 +00:00
Katherine Parry
b54d84195f added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
slmnemo
ded2631567 Removed big64.txt reference, fixing a warning 2022-06-23 14:39:53 -07:00
David Harris
2c4b86c703 Fixed typo in clint 2022-06-23 21:27:46 +00:00
David Harris
ceddc99ac9 Reset mtimecmp in clint 2022-06-23 21:20:55 +00:00
Katherine Parry
49067792dc fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
4a6dee5926 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
Madeleine Masser-Frye
0161683945 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 20:31:06 +00:00
Madeleine Masser-Frye
fe31ee92e8 switched comparator to dc flip version 2022-06-21 20:30:33 +00:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Katherine Parry
93906b9457 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-15 22:58:42 +00:00
Katherine Parry
e121dcd4af postprocess out of fpu critical path 2022-06-15 22:58:33 +00:00
Madeleine Masser-Frye
c2493168b6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-15 18:30:27 +00:00
Madeleine Masser-Frye
76e30ed8ab cleanup, plots for paper 2022-06-15 18:28:36 +00:00
Katherine Parry
11b252a735 some synth fpu optimizations 2022-06-14 23:58:39 +00:00
Katherine Parry
998876ce49 removed false critical path from fpu 2022-06-14 16:50:46 +00:00
Katherine Parry
566001e07b fixed acciedental critical path in FPU 2022-06-14 00:02:38 +00:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
David Harris
8ea484a343 Cleanup on RAM module 2022-06-13 19:37:43 +00:00
David Harris
b7a7ca6eac Typo in gpio reset 2022-06-13 19:37:05 +00:00
slmnemo
915b8e2adb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:27:23 -07:00
slmnemo
7b704f8db0 Merge branch 'cacheburstmode' into main. 
Cache burst mode is now working! It also uses the new RAM.
 2022-06-13 12:26:18 -07:00
slmnemo
98c07ce2c0 Added more comments 2022-06-13 12:26:08 -07:00
David Harris
ccd16210bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 19:26:07 +00:00
David Harris
e9ef9a5cb8 Fixed XOR logic in GPIO 2022-06-13 19:26:03 +00:00
slmnemo
3d715a098c Added comment about name of LSUBusInit/Lock signal 2022-06-13 10:56:02 -07:00
slmnemo
cadd62e49f Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals 2022-06-10 20:43:56 -07:00
slmnemo
beb4317e68 Added comments to signals added so the bus is easier to analyze 2022-06-10 20:30:04 -07:00
slmnemo
b7357efc6b Fixed failed regression state by only enabling counting when doing cached operations 2022-06-10 20:00:09 -07:00
slmnemo
63ed390c90 Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01. 2022-06-10 19:10:01 -07:00
Madeleine Masser-Frye
422bd2043f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-10 21:11:47 +00:00
Madeleine Masser-Frye
7cdf9cd4d3 added 'd' suffix to muxes for data-critical synths 2022-06-10 21:11:05 +00:00
slmnemo
dc11066ff2 Passed Regression: Seems to work perfectly fine 2022-06-09 18:21:13 -07:00
slmnemo
ec7cdee0f3 Merge branch 'main' into cacheburstmode 2022-06-09 17:51:03 -07:00
slmnemo
5a6eae214a ? 2022-06-09 17:50:47 -07:00
slmnemo
3e8d3bae88 Changes made on 9th Jun 2022-06-09 17:33:51 -07:00
slmnemo
4ff105f18c Fixed lint error 2022-06-09 17:22:04 -07:00
David Harris
c836f37a08 New RAM for further testing 2022-06-09 23:50:43 +00:00
David Harris
dd4fa7c682 qslc_r4a2 generator 2022-06-09 17:26:47 +00:00
slmnemo
0d04751c77 Fixed error when doing uncached accesses where HTRANS was always 2 2022-06-08 18:58:07 -07:00
slmnemo
81d373c7ab Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request. 2022-06-08 17:34:02 -07:00
Madeleine Masser-Frye
0e64494e46 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-09 00:08:15 +00:00
Madeleine Masser-Frye
a58a756076 added one bit muxes for data critical synths 2022-06-09 00:06:12 +00:00
slmnemo
11924bdd9b Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending 2022-06-08 15:59:15 -07:00
slmnemo
e17ee3073e Fixed ifu displaying LSU bus state in wave.do 2022-06-08 15:30:32 -07:00
slmnemo
315c2f0669 Working version: Fixed error where Word count would always increment even without AHB to bus ACK 2022-06-08 15:29:32 -07:00
slmnemo
054cf5f7b0 Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
DTowersM
6402b2dec4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-08 16:28:18 +00:00
DTowersM
6944996329 added #1 delays to Stalls and Flushes in hazard unit 2022-06-08 16:28:09 +00:00
slmnemo
284e0395a0 Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42 Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
David Harris
5240bd1c90 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
3c8eafc8ee Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
9e5ab4d378 Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
slmnemo
6d36150c3d Fixed off-by-one error in busdp capture 2022-06-07 19:36:39 +00:00
slmnemo
73e0c1c07f Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00
Katherine Parry
8fa0fc4229 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
Madeleine Masser-Frye
56a053fc3d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye
31e9d0a41a added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
Katherine Parry
6b39b8c702 fixed compilation errors 2022-06-03 15:34:17 +00:00
Katherine Parry
03280c0f9c added createallvectors 2022-06-02 21:56:05 +00:00
Katherine Parry
9a09ee3a35 fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
David Harris
1d8bc2dc1b Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
David Harris
faa15b1f8d Cleaned up comments in controller 2022-06-02 15:48:33 +00:00
David Harris
c7ec9282fe Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
Katherine Parry
e42afbfb30 paramerterized some small fma units 2022-06-01 23:34:29 +00:00
Katherine Parry
dd19e55b8f unpacker optimizations 2022-06-01 16:52:21 +00:00
slmnemo
446ad498aa Fixed double assignment on LSUBurstType 2022-06-01 01:04:49 +00:00
slmnemo
cf05fec9c7 Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access 2022-05-31 16:33:05 -07:00
slmnemo
a86c4d5ff3 Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode 2022-05-31 15:57:55 -07:00
slmnemo
9ad1a42886 Redid the FSM to prepare for burst mode implementation 2022-05-31 15:57:42 -07:00
David Harris
475a84491e Unpackinput cleanup 2022-05-31 22:31:21 +00:00
David Harris
f9533fea1a Removed normalized output from unpack and simplified interface 2022-05-31 21:32:31 +00:00
David Harris
0d0a9cba66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 21:12:45 +00:00
David Harris
aa7b0616e4 ../src/privileged/csrc.sv 2022-05-31 21:12:17 +00:00
Katherine Parry
f6ac33ce8a reorginized unpackinput signals 2022-05-31 17:40:34 +00:00
Katherine Parry
4ed7933aa3 added unpackinput.sv 2022-05-31 16:18:50 +00:00
David Harris
788fe406b5 Moved delegation logic from privmode to trap to simplify interface 2022-05-31 14:58:11 +00:00
David Harris
0cfe9e3373 Removed unused fp add and convert modules 2022-05-29 23:07:56 +00:00
Katherine Parry
950a17bef5 fixed lint error 2022-05-28 10:20:13 -07:00
slmnemo
f78fa3b9b9 Reverted incorrect Ack 2022-05-28 10:06:26 +00:00
David Harris
b04e9ac1f6 fixed merge conflicts 2022-05-28 09:44:55 +00:00
David Harris
4237bb7abd Added comments to some files, added a+b = 0 detector to comparator.sv 2022-05-28 09:41:48 +00:00
Katherine Parry
9c58c63864 removed unused signal from FMA 2022-05-27 16:47:56 -07:00
Katherine Parry
a0ff98042c unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
95b506c5e0 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
Katherine Parry
1be91753fe moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
Katherine Parry
c6d79cd718 Removed guard bit from fma rounding 2022-05-27 08:23:46 -07:00
slmnemo
bc17f883d4 changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word 2022-05-26 18:41:27 -07:00
slmnemo
847c7930c4 added LSUBurstDone signal to signal when a burst has finished 2022-05-26 16:29:13 -07:00
Katherine Parry
9d281b2604 fcvt.sv paramaterized 2022-05-26 20:48:22 +00:00
slmnemo
80fc716cd7 Added signal to monitor HBURST and comments for each burst in busdp 2022-05-26 13:35:49 -07:00
slmnemo
08430a1e85 added burst size signals to the IFU, EBU, LSU, and busdp 2022-05-25 18:02:50 -07:00
slmnemo
cebf93cf9c idk lol it says this has an unadded change 2022-05-25 17:17:49 -07:00
Katherine Parry
f3b28b988b added fcvt.sv 2022-05-26 00:10:51 +00:00
Katherine Parry
f35450207f single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
81a869c921 ppaAnalyze: docstrings and tsmc28 plotting 2022-05-25 13:52:20 +00:00
Madeleine Masser-Frye
dd4997bd1b added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
Ross Thompson
b70baed214 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 23:54:33 -05:00
Ross Thompson
e2cf941a23 Possible plic fix? 2022-05-22 23:47:01 -05:00
Madeleine Masser-Frye
d91fd44ea5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-22 23:23:39 +00:00
Madeleine Masser-Frye
dbe4b4bafa added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Ross Thompson
bcb4ebf888 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 10:55:33 -05:00
Ross Thompson
c4f1a0362b Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
92a2ad02db Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Madeleine Masser-Frye
39a3bf5cdc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-05-21 09:53:31 +00:00
Madeleine Masser-Frye
b832a21b73 ppa updates 
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
 2022-05-21 09:53:26 +00:00
Katherine Parry
5d34db85b2 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
af0300c3d7 added documentation for ahblite burst types to ahblite.sv 2022-05-19 18:31:46 -07:00
Katherine Parry
ab1f088672 fixed lint warning 2022-05-19 20:34:06 +00:00
Katherine Parry
6f2d8c24ad Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
mmasserfrye
bab7335bee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-19 20:24:57 +00:00
mmasserfrye
d34f4a7c3c updated synth plotting and regression 2022-05-19 20:24:47 +00:00
Katherine Parry
738bbf6479 Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
mmasserfrye
84422f3859 added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
mmasserfrye
12c42cd507 adapted shifter in ppa.sv for widths beside 32 and 64 
modified plotting and regression in ppaAnalyze.py
 2022-05-18 16:08:40 +00:00
Ross Thompson
b853c4ba47 Updated fpga debugger. 2022-05-17 23:04:01 -05:00
mmasserfrye
2254a8218d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 01:11:58 +00:00
mmasserfrye
d34a942eb2 added 8 and 128 bit versions, adjusted alu 2022-05-17 01:11:43 +00:00
slmnemo
8c8a7daec2 Fixed grammar on two comments in bpred.sv 2022-05-16 22:41:18 +00:00
mmasserfrye
68a70ed8ff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
resolved merge conflict
 2022-05-16 15:42:59 +00:00
mmasserfrye
b82520237c tuning modules for ppa 2022-05-16 15:39:15 +00:00
David Harris
48e89485dd Cause simplification 2022-05-12 23:47:21 +00:00
David Harris
9651ced9bb Cause simplification 2022-05-12 23:39:10 +00:00
David Harris
2f283d9654 Cause simplification 2022-05-12 23:37:40 +00:00
David Harris
f5f1870077 Cause simplification 2022-05-12 23:33:35 +00:00
David Harris
5b7cccbc4b Cause simplification 2022-05-12 23:33:22 +00:00
David Harris
581d841653 Cause simplification 2022-05-12 23:29:35 +00:00
David Harris
2a3f545e0c Cause simplification 2022-05-12 23:27:02 +00:00
David Harris
c2b9fc0d8e trap/csr cleanup 2022-05-12 22:26:21 +00:00
David Harris
292d1f33da More trap/csr simplification 2022-05-12 22:06:03 +00:00
David Harris
662fffa830 More trap/csr simplification 2022-05-12 22:04:20 +00:00
David Harris
16b86c199c More trap/csr simplification 2022-05-12 22:00:23 +00:00
David Harris
5f358a37c6 More trap/csr simplification 2022-05-12 21:55:50 +00:00
David Harris
21ac969c7d Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00
David Harris
072c464dc1 Simplified MTVAL logic 2022-05-12 21:36:13 +00:00
David Harris
14f9f41d2d Partitioned privileged pipeline registers into module 2022-05-12 20:45:45 +00:00
David Harris
78448c7053 privileged cleanup 2022-05-12 20:21:33 +00:00
mmasserfrye
31f372e7b3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 20:20:40 +00:00
mmasserfrye
a10b8e47af cleaned lint for ppa.sv 2022-05-12 20:20:05 +00:00
David Harris
dd61afb7dc Formatting cleanup 2022-05-12 18:37:47 +00:00
mmasserfrye
01685b982c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 18:08:20 +00:00
mmasserfrye
b089ee26ee renamed madzscript, modified ppa.sv alu and shifter 2022-05-12 18:05:02 +00:00
David Harris
fde8375fbd Moved Breakpoint and Ecall fault logic into privdec 2022-05-12 16:45:53 +00:00
David Harris
2ceed15bd5 Moved TLB Flush logic into privdec 2022-05-12 16:41:52 +00:00
David Harris
1e5d94bbab Moved WFI timeout into privdec 2022-05-12 16:22:39 +00:00
David Harris
39ceb3a550 Partitioned privilege mode fsm into new module 2022-05-12 16:16:42 +00:00
David Harris
e81e530f68 More signal cleanup 2022-05-12 15:39:44 +00:00
David Harris
ce24c080d5 More unused signal cleanup 2022-05-12 15:26:08 +00:00
David Harris
5670f77de2 More unused signal cleanup 2022-05-12 15:21:09 +00:00
David Harris
4edf9b6355 More unused signal cleanup 2022-05-12 15:15:30 +00:00
David Harris
1aa3e65bae Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
David Harris
e2e63ca9a8 Clean up unused signals 2022-05-12 14:49:58 +00:00
David Harris
f17501ed8c Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
545d46acb9 Simplifed mstatus.TSR handling 2022-05-12 14:09:52 +00:00
David Harris
1e7401daa0 Fixed typo in csrm 2022-05-12 06:55:39 -07:00
mmasserfrye
999754801c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 07:24:04 +00:00
mmasserfrye
6cba6a92ba filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
David Harris
9999f69922 Added MCONFIGPTR CSR hardwired to 0 2022-05-12 04:31:45 +00:00
David Harris
9dd378098f merged ppa.sv 2022-05-11 18:14:16 +00:00
David Harris
1f761c4e06 PPA script progress 2022-05-11 18:11:51 +00:00
mmasserfrye
552a55d631 ed 
modified ppa.sv
 2022-05-11 16:22:12 +00:00
David Harris
8166fd772e Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
137b411bea Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
490902a655 Updated PPA experiment 2022-05-10 23:09:42 +00:00
David Harris
bb24aebebd Initial PPA study 2022-05-10 20:48:47 +00:00
David Harris
04fd22aeb0 endian swapper 2022-05-08 06:51:50 +00:00
David Harris
4f1b0fdc64 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
David Harris
1a5bfcf078 Fixed bug in delegated interrupts not being taken 2022-05-08 04:50:27 +00:00
David Harris
a516f89f22 WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
David Harris
412d4656ed Zero'd wfiM when ZICSR not supported to fix hang in E tests 2022-05-05 15:32:13 +00:00
David Harris
7f42ff06d2 SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
David Harris
f436e93fc5 SFENCE.VMA should be illegal in user mode 2022-05-05 14:59:52 +00:00
David Harris
9b7aab122e wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
David Harris
1a7599ce94 Changed WFI to stall pipeline in memory stage 2022-05-05 02:03:44 +00:00
David Harris
8a43d6099b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-03 18:32:04 +00:00
David Harris
4b91fddc0a Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
3efbd2565a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
20bbe43a23 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
1166c40059 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
bcd8728b3e Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
b4a422f771 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
057524b840 Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
9e50c3440d sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
0df73d203b Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
David Harris
9e47fca2b7 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00
David Harris
515270a8cf Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
David Harris
cce0a421be Checked in torture.tv 2022-04-27 13:06:24 +00:00
David Harris
9d82232c14 Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
33875b20b5 fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
David Harris
0957b7040d Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
1a8369b02b Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
David Harris
142636173e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00