cvw/pipelined/src
2022-09-13 17:51:55 -05:00
..
cache pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
ebu pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
fpu Moved C to shift before rather than after using in an iteration 2022-09-08 16:05:53 -07:00
generic Factored out aplusbeq0 unit 2022-09-07 11:36:35 -07:00
hazard Added comments about planned changes. 2022-08-29 09:48:00 -05:00
ieu Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
ifu Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
lsu Renamed signals in the LSU. 2022-09-13 11:47:39 -05:00
mmu Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
uncore Added generate around the longer latency version of the ram_ahb.sv 2022-09-06 09:21:03 -05:00
wally Removed old signals. 2022-08-31 09:50:39 -05:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00