David Harris 35d0a951d2 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.		2022-08-27 20:31:09 -07:00
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cache	Fixed rv32e LSU and IFU issues	2022-08-25 20:02:38 -07:00
ebu	Separated busdp for cache from simpler logic for no cache	2022-08-25 17:54:04 -07:00
fpu	Only stall FPU to IEU on convert instructions with dependencies	2022-08-23 12:57:18 -07:00
generic	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 09:52:49 -07:00
hazard	Simplified FPU-LSU interface to skip IEU	2022-08-22 13:28:51 -07:00
ieu	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
ifu	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
lsu	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
mmu	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
uncore	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
wally	FIxed wallypipelinedsoc merge conflict	2022-08-25 15:36:47 -07:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00