Ross Thompson b2f71b8255 Modified LSU to support DTIM without CSRs.		2022-10-11 14:05:20 -05:00
..
cache	Reordered the eviction and fetch in cache so it follows a more logical order.	2022-10-04 17:36:07 -05:00
ebu	Fixed bug in EBU.	2022-10-05 14:51:12 -05:00
fpu	New fdivsqrtqsel4cmp module based on comparators rather than table lookup	2022-10-09 04:47:44 -07:00
generic	changed always_ff to always in sram1p1rw to fix testbench complaint	2022-09-25 19:56:40 -07:00
hazard	Added comments about planned changes.	2022-08-29 09:48:00 -05:00
ieu	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
ifu	Fixed first problem with the rv64i IROM.	2022-10-11 11:35:40 -05:00
lsu	Modified LSU to support DTIM without CSRs.	2022-10-11 14:05:20 -05:00
mmu	Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.	2022-10-05 14:51:02 -05:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.	2022-10-02 16:21:21 -05:00
uncore	Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.	2022-09-29 11:54:03 -05:00
wally	Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing	2022-10-10 07:12:37 -07:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00