cvw/pipelined/src
2022-08-25 04:28:25 -07:00
..
cache Updated fpga test bench. 2022-08-21 15:59:54 -05:00
ebu renamed GrantData to LSUGrant 2022-08-22 13:47:19 -07:00
fpu Only stall FPU to IEU on convert instructions with dependencies 2022-08-23 12:57:18 -07:00
generic removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
hazard Simplified FPU-LSU interface to skip IEU 2022-08-22 13:28:51 -07:00
ieu Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
ifu Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM 2022-08-25 04:06:27 -07:00
lsu Minor name cleanups 2022-08-25 04:28:25 -07:00
mmu Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
uncore Stripped write capaibilty out of rom_ahb 2022-08-24 17:23:08 -07:00
wally Fixed FPU-IEU forwarding stall 2022-08-23 14:14:41 -07:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00